參數(shù)資料
型號(hào): XC2S30-6VQ100C
廠(chǎng)商: Xilinx Inc
文件頁(yè)數(shù): 7/99頁(yè)
文件大小: 0K
描述: IC FPGA 2.5V C-TEMP 100-PQFP
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-II
LAB/CLB數(shù): 216
邏輯元件/單元數(shù): 972
RAM 位總計(jì): 24576
輸入/輸出數(shù): 60
門(mén)數(shù): 30000
電源電壓: 2.375 V ~ 2.625 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
15
R
Figure 9 is a diagram of the Spartan-II family boundary scan
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins
contributes all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 10.
BSDL (Boundary Scan Description Language) files for
Spartan-II family devices are available on the Xilinx
website, in the Downloads area.
Figure 9: Spartan-II Family Boundary Scan Logic
D
Q
D
Q
IOB
M
U
X
Bypass
Register
IOB
TDO
TDI
IOB
1
0
1
0
1
0
1
0
1
0
sd
LE
DQ
D
Q
D
Q
1
0
1
0
1
0
1
0
DQ
LE
sd
LE
DQ
sd
LE
DQ
IOB
D
Q
1
0
DQ
LE
sd
IOB.T
DATA IN
IOB.I
IOB.Q
IOB.T
IOB.I
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
DATAOUT
UPDATE
EXTEST
DS001_09_032300
Instruction Register
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