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參數(shù)資料
| 型號： | XC2S30-6VQ100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 66/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2.5V C-TEMP 100-PQFP |
| 標準包裝： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 216 |
| 邏輯元件/單元數(shù)： | 972 |
| RAM 位總計： | 24576 |
| 輸入/輸出數(shù)： | 60 |
| 門數(shù)： | 30000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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DS001-4 (v2.8) June 13, 2008
Module 4 of 4
Product Specification
69
2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
Introduction
This section describes how the various pins on a
Spartan-II FPGA connect within the supported component
packages, and provides device-specific thermal
characteristics. Spartan-II FPGAs are available in both
standard and Pb-free, RoHS versions of each package,
with the Pb-free version adding a “G” to the middle of the
package code. Except for the thermal characteristics, all
information for the standard package applies equally to the
Pb-free package.
Pin Types
Most pins on a Spartan-II FPGA are general-purpose,
user-defined I/O pins. There are, however, different
functional types of pins on Spartan-II FPGA packages, as
outlined in Table 35.
99
Spartan-II FPGA Family:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
Product Specification
R
Table 35: Pin Definitions
Pin Name
Dedicated
Direction
Description
GCK0, GCK1, GCK2,
GCK3
No
Input
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
M0, M1, M2
Yes
Input
Mode pins are used to specify the configuration mode.
CCLK
Yes
Input or Output
The configuration Clock I/O pin. It is an input for slave-parallel and slave-serial
modes, and output in master-serial mode.
PROGRAM
Yes
Input
Initiates a configuration sequence when asserted Low.
DONE
Yes
Bidirectional
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output may be open drain.
INIT
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being cleared. This pin
becomes a user I/O after configuration.
BUSY/DOUT
No
Output
In Slave Parallel mode, BUSY controls the rate at which configuration data is
loaded. This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to downstream devices in
a daisy-chain. This pin becomes a user I/O after configuration.
D0/DIN, D1, D2, D3, D4,
D5, D6, D7
No
Input or Output
In Slave Parallel mode, D0-D7 are configuration data input pins. During
readback, D0-D7 are output pins. These pins become user I/Os after
configuration unless the Slave Parallel port is retained.
In serial modes, DIN is the single data input. This pin becomes a user I/O after
configuration.
WRITE
No
Input
In Slave Parallel mode, the active-low Write Enable signal. This pin becomes
a user I/O after configuration unless the Slave Parallel port is retained.
CS
No
Input
In Slave Parallel mode, the active-low Chip Select signal. This pin becomes a
user I/O after configuration unless the Slave Parallel port is retained.
TDI, TDO, TMS, TCK
Yes
Mixed
Boundary Scan Test Access Port pins (IEEE 1149.1).
VCCINT
Yes
Input
Power supply pins for the internal core logic.
VCCO
Yes
Input
Power supply pins for output drivers (subject to banking rules)
VREF
No
Input
Input threshold voltage pins. Become user I/Os when an external threshold
voltage is not needed (subject to banking rules).
GND
Yes
Input
Ground.
IRDY, TRDY
No
See PCI core
documentation
These signals can only be accessed when using Xilinx PCI cores. If the
cores are not used, these pins are available as user I/Os.
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