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參數(shù)資料
型號(hào)： XA3SD3400A-4FGG676I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 13/58頁(yè)
文件大?。?/td> 0K
描述： SPARTAN-3ADSP FPGA 3400K 676FBGA
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 40
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計(jì)： 2322432
輸入/輸出數(shù)： 469
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
20
Hold Times
TIOICKP
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the point
where data must be held at the Input pin. No
Input Delay is programmed.
LVCMOS25(3)
0
XA3SD1800A
–0.52
ns
XA3SD3400A
–0.56
ns
TIOICKPD
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the point
where data must be held at the Input pin. The
Input Delay is programmed.
LVCMOS25(3)
1
XA3SD1800A
–1.40
ns
2
–2.11
ns
3
–2.48
ns
4
–2.77
ns
5
–2.62
ns
6
–3.06
ns
7
–3.42
ns
8
–3.65
ns
1
XA3SD3400A
–1.31
ns
2
–1.88
ns
3
–2.44
ns
4
–2.89
ns
5
–2.83
ns
6
–3.33
ns
7
–3.63
ns
8
–3.96
ns
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR control input on
IOB
–
All
1.61
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
3.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 21: Sample Window (Source Synchronous)
Symbol
Description
Max
Units
TSAMP
Setup and hold
capture window of
an IOB flip-flop
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
Answer Record 30879
ps
Table 20: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
IFD_DELAY
_VALUE
Device
Speed Grade: -4
Units
Min
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