參數(shù)資料
型號(hào)： WED3DL3216V10BI
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 16M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119
封裝： 17 X 23 MM, MO-163, BGA-119
文件頁(yè)數(shù)： 24/27頁(yè)
文件大?。?/td> 989K
代理商： WED3DL3216V10BI
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WED3DL3216V
November, 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
COMMAND TRUTH TABLE
NOTES:
1.
All of the SDRAM operations are dened by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.
2.
Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected.
3.
During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4.
During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5.
The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations,
therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode
entry and exit.
Function
CKE
CE#
RAS# CAS# WE# DQM
BA
A0-A10 A12, A11,
Notes
Previous
Cycle
Current
Cycle
Register Mode Register Set
H
X
L
X
OP CODE
Refresh Auto Refresh (CBR)
H
L
H
X
Entry Self Refresh
H
L
H
X
Precharge Single Bank Precharge
H
X
L
H
L
X
BA
L
X
2
Precharge all Banks
H
X
L
H
L
X
H
X
Bank Activate
H
X
L
H
X
BA
Row Address
2
Write
H
X
L
H
L
X
BA
L
Column
2
Write with Auto Precharge
H
X
L
H
L
X
BA
H
Column
2
Read
H
X
L
H
L
X
BA
L
Column
2
Read with Auto Precharge
H
X
L
H
L
H
X
BA
H
Column
2
Burst Termination
H
X
L
H
L
X
3
No Operation
H
X
L
H
X
Device Deselect
H
X
H
X
Clock Suspend/Standby Mode
L
X
4
Data Write/Output Disable
H
X
L
X
5
Data Mask/Output Disable
H
X
H
X
5
Power Down Mode
Entry
X
L
H
X
6
Exit
X
H
X
6
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