參數(shù)資料
型號(hào)： W25X80AVDAIZ
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 1M X 8 FLASH 2.7V PROM, PDIP8
封裝： 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8
文件頁(yè)數(shù)： 18/45頁(yè)
文件大?。?/td> 1344K
代理商： W25X80AVDAIZ
W25X10A, W25X20A, W25X40A, W25X80A
Publication Release Date: August 7, 2009
- 25 -
Revision F
10.2.13 Chip Erase (C7h or 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure
14.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction
will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed
if any page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory
Protection table).
Figure 14. Chip Erase Instruction Sequence Diagram
相關(guān)PDF資料
PDF描述
W25X80ALSSIG 1M X 8 FLASH 2.7V PROM, PDSO8
W25X40ALDAIZ 512K X 8 FLASH 2.7V PROM, PDIP8
W25X10ALSNIG 128K X 8 FLASH 2.7V PROM, PDSO8
W27C257P-12 32K X 8 EEPROM 12V, 120 ns, PQCC32
W27L01-70 128K X 8 EEPROM 12V, 70 ns, PDIP32
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