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參數(shù)資料
| 型號(hào)： | W25X80AVDAIZ |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 8 FLASH 2.7V PROM, PDIP8 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 10/45頁 |
| 文件大?。?/td> | 1344K |
| 代理商： | W25X80AVDAIZ |
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W25X10A, W25X20A, W25X40A, W25X80A
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10.2.6 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable
instruction must previously have been executed for the device to accept the Write Status Register
Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by
driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as
illustrated in figure 7. The Status Register bits are shown in figure 3 and described earlier in this
datasheet.
Only non-volatile Status Register bits SRP, TB, BP2, BP1 and BP0 (bits 7, 5, 4, 3 and 2) can be
written to. All other Status Register bit locations are read-only and will not be affected by the Write
Status Register instruction.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed
Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While
the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed
to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a
0 when the cycle is finished and ready to accept other instructions again. After the Write Register
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0) to be set
for protecting all, a portion, or none of the memory from erase and program instructions. Protected
areas become read-only (see Status Register Memory Protection table). The Write Status Register
instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction
with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0
state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a
1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is
high the Write Status Register instruction is allowed.
Figure 7. Write Status Register Instruction Sequence Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W25X80ALSSIG | 1M X 8 FLASH 2.7V PROM, PDSO8 |
| W25X40ALDAIZ | 512K X 8 FLASH 2.7V PROM, PDIP8 |
| W25X10ALSNIG | 128K X 8 FLASH 2.7V PROM, PDSO8 |
| W27C257P-12 | 32K X 8 EEPROM 12V, 120 ns, PQCC32 |
| W27L01-70 | 128K X 8 EEPROM 12V, 70 ns, PDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25X80AVSNIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI |
| W25X80AVSSIG | 功能描述:IC FLASH 16MBIT 100MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:SpiFlash® 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| W25X80AVZPIG | 功能描述:IC FLASH 16MBIT 100MHZ 8WSON RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:SpiFlash® 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| W25X80L | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI |
| W25X80LDAC | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI |
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