參數(shù)資料
型號(hào)： W25Q16DWSFIG
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 16M X 1 SPI BUS SERIAL EEPROM, PDSO16
封裝： 0.300 INCH, GREEN, PLASTIC, SOIC-16
文件頁數(shù)： 28/83頁
文件大?。?/td> 1268K
代理商： W25Q16DWSFIG
W25Q16DW
- 34 -
M7-0
/CS
CLK
10.2.16 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 15a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 15b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4
= 1 and return the device to normal operation.
Figure 15a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4
≠10, SPI Mode)
Mode 0
Mode 3
0
1
IO
0
IO
1
IO
2
IO
3
2
3
4
5
20
16
12
8
21
17
22
18
23
19
13
9
14
10
15
11
A23-16
6
7
8
9
4
0
5
1
6
2
7
3
A15-8
A7-0
Byte 1
Byte 2
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
10
11
12
13
14
4
5
6
7
15
IOs switch from
Input to Output
Byte 3
16
17
18
19
20
21
22
23
Dummy
Instruction (EBh)
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