參數(shù)資料
型號: UT1553
廠商: Electronic Theatre Controls, Inc.
英文描述: BCRTM
中文描述: BCRTM
文件頁數(shù): 38/61頁
文件大小: 2024K
代理商: UT1553
BCRTM-43
MCLKD2
ADDRESS
DATA
AEN
BURST
DMA GRANT RECOGNIZED ON THIS EDGE
THMC1+10
40
SYMBOL
PARAMETER
MIN
MAX
UNITS
-2
THMC1-10
MCLK-20
ns
0
2x-2MCLK
MCLK
45
4xMCLK
6xMCLK
MCLK+20
3.5 (1.9)
MCLK = period of the memory clock cycle.
BURST signal is for multiple-word DMA accesses.
THMC1 is equivalent to the positive phase of MCLK (see figure 27).
-10
ns
10
s
0
1.9 (0.8)
s
ns
-5
+5
DMAR
DMAG
DMACK
TSCTL
MEMCSO
tSHL1
tPW2
tOOZL1
tPHL4
tPHL1
tPHL2
tPZL1
tPHL3
RWR/RRD
2
tSHL1
6
DMACK
↓ to DMAR High Impedance RAD
NON-RAD
DMAG
↓ to DMACK3
DMAG
↓ to TSCTL
TSCTL
↓ to ADDRESS valid RAD
NON-RAD
RWR/RRD
↑ to DMACK
TSCTL
↓ to RWR/RRD
DMAG
↓ to DMAG
DMAR
↓ to BURST
DMAR
↓ to DMAG5
DMAR
↓ to DMAG4
Notes:
1. Guaranteed by test.
2. See figures 27 & 28 for detailed DMA read and write timing.
3. DMAG must be asserted at least 45ns prior to the rising edge of MCLKD2 in order to be recognized for the next MCLKD2 cycle.
If DMAG is not asserted at least 45ns prior to the rising edge of MCLKD2, DMAG is not recognized until the following MCL
KD2 cycle.
4. Provided MCLK = 12MHz. Number in parentheses indicates the longestDMAR
↓ toDMAG↓allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
5. Provided MCLK = 6MHz. Number in parentheses indicates the longest DMAR
↓ DMAG↓ allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
6. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.
tPHL1
tPHL2
1
tPZL1
6
tHLH2
tPHL3
tPW2
1
tOOZL1
tPHL4
tHLH2
Figure 26. BURST DMA Timing
10
0
40
ns
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