參數(shù)資料
型號(hào)： UT1553
廠商： Electronic Theatre Controls, Inc.
英文描述： BCRTM
中文描述： BCRTM
文件頁(yè)數(shù)： 24/61頁(yè)
文件大?。?/td> 2024K
代理商： UT1553
BCRTM-30
7.1 BC Functional Operation
The Bus Controller off-loads the host computer of many
functions needed to coordinate 1553B bus data transfers.
Special architectural features provide message- by-message
flexibility. In addition, a programmable interrupt scheme,
programmable intermessage timing delays, and internal
registers enhance the BCRTM’s operation.
The host determines the first Command Block by setting the
initial starting address in the current Command Block
Register. Once set, the BCRTM updates the current
Command Block Register with the next Command Block
Address. The BCRTM then executes the sequential
Command Blocks and counts out message delays (where
programmed) until it encounters the last Command Block
listed (indicated by the End of List bit in the control word).
Interrupts are asserted when enabled events occur (see
section 9.0, Exception Handling and Interrupt Logging).
The functions and their programming instructions are
described below. The registers also contain many
programmable functions and function parameters.
BC Command Block Definition
Each Command Block contains (see figure 10):
A. Head Pointer. Host-written, this location can contain the address of the previous Command Block’s Head Pointer.
The BCRTM does not access this location.
B. Control Word. Host-written, the Control Word contains bit-selectable options and a Message Error bit the
BCRTM provides (see figure 13). The bit definitions follow.
Bit
Number
Description
BIT 15
Message Error. The BCRTM sets this bit when it detects an invalid RT response as defined in
MIL-STD 1553B.
BIT 14
Skip. When set, this bit instructs the BCRTM to skip this Command Block and execute the next.
BIT 13
Interrupt and Continue. If set, a Standard Interrupt is asserted when this block is addressed; operation,
however, continues. Note that this interrupt must also be enabled by setting bit 0 of Register 9.
BIT 12
Polling Enable. Enables the BCRTM’s polling operation.
BIT 11
Auto Retry Enable. When set, the Auto Retry function, governed by the global parameters in the Control
Register, is enabled for this message.
BIT 10
End of List. Set by the CPU, this bit indicates that the BCRTM, upon completion of the current message,
will halt and assert a High-Priority Interrupt. The interrupt must also be
enabled in the High-Priority Interrupt Enable Register.
BIT 9
RT-RT. Set by the CPU, this indicates that this Command Block transacts an RT-RT transfer.
‘TIME DELAY’
TRANSFER
RT-RT
MONITOR
TRANSFER
RT-RT
LIST
OF
END
ENABLE
RETRY
AUTO
ENABLE
POLLING
CONTINUE
AND
INTERRUPT
ERROR
MESSAGE
SKIP
15
14
13
12
11
10
9
8
7
0
Figure 13. Command Word
Figure 14. BC Timing Delays
MESSAGE #1
MESSAGE #2
MESSAGE #3
TDELAY1
TDELAY2
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