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參數(shù)資料
| 型號(hào)： | UT1553 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | BCRTM |
| 中文描述： | BCRTM |
| 文件頁(yè)數(shù)： | 2/61頁(yè) |
| 文件大?。?/td> | 2024K |
| 代理商： | UT1553 |
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BCRTM-10
NAME
TYPE
ACTIVE
DESCRIPTION
TAO
14
L2
TO
TAZ
13
K3
TO
TBO
18
K6
TO
--
TBZ
17
L4
TO
--
BIPHASE OUTPUTS
Transmit Channel A One. This is the Manchester-encoded
true output to be connected to the Channel A bus transmitter
input. This signal is idle low.
Transmit Channel A Zero. This is the Manchester-encoded
complementary output to be connected to the Channel A bus
transmitter input. This signal is idle low.
Transmit Channel B One. This is the Manchester-
encoded true output to be connected to the Channel B bus
transmitter input. This signal is idle low.
Transmit Channel B Zero. This is the Manchester-encoded
complementary output to be connected to the Channel B bus
transmitter input. This signal is idle low.
PIN NUMBER
LCC
PGA
56
A10
ZL
57
67
58
A9
B5
B8
AL
ZL
TTO
TI
TO
TTO
NAME
TYPE
ACTIVE
DESCRIPTION
DMA SIGNALS
55
B9
TO
AL
BURST
74
A1
TO
AH
DMA Request. The BCRTM issues this signal when access to
RAM is required. It goes inactive after receiving a DMAG
signal.
DMAR
DMAG
DMAGO
DMACK
TSCTL
DMA Grant Out. If DMAG is received but not needed, it
passes through to this output.
DMA Acknowledge. The BCRTM asserts this signal to confirm
receipt of DMAG, it stays low until memory access is complete.
PIN NUMBER
LCC
PGA
DMA Grant. This input to the BCRTM allows the
BCRT to access RAM. It is recognized 45ns before the rising
edge of MCLKD2.
Three-State Control. This signal indicates when the
BCRTM is actually accessing memory. The host subsystem’s
address and data lines must be in the high-impedance state when
the signals active. This signal assists in placing the external data
and address buffers into the high-impedance state.
Burst (DMA Cycle). This indicates that the current
DMA cycle transfers at least two words; worst case is five words
plus a “dummy” word.
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