參數(shù)資料
型號(hào)： UPD98401A
廠商： NEC Corp.
英文描述： ATM SAR CHIP
中文描述： 自動(dòng)柜員機(jī)特區(qū)芯片
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 216K
代理商： UPD98401A
Data Sheet S12100EJ3V0DS00
14
μ
PD98401A
1.5 JTAG Boundary Scan Pins
Pin Name
Pin No.
I/O
I/O Level
Function
JDI
201
I
TTL
JTAG Test Data Input.
The JDI pin is used to input data to the JTAG boundary scan circuit
register.
Normally, fix this pin to high or low level.
JDO
200
O
3-state
CMOS
JTAG Test Data Output.
The JDO pin is used to output data from the JTAG boundary scan
circuit register. It changes output at the falling edge of the clock input
to the JCK pin.
Normally, leave this pin open.
JCK
197
I
TTL
JTAG Test Clock.
This pin is used to supply a clock to the JTAG boundary scan circuit
register.
Normally, fix this pin to a high or low level.
JMS
202
I
TTL
JTAG Test Mode Select.
Normally, fix this pin to a high or low level.
JRST_B
203
I
TTL
JTAG Test Reset.
This pin initializes the JTAG boundary scan circuit register. Normally,
fix this pin to a low level.
1.6 Test Pin
Pin Name
Pin No.
I/O
I/O Level
Function
TRF_B
189
I
TTL
This pin is used to test the internal circuitry of the chip.
0: Normal operation
1: Test
Normally, directly connect this pin to ground and fix it to a low level.
1.7 Power Supply and Ground Pins
Pin Name
Pin No.
I/O
Function
V
DD
15, 27, 30, 34, 41, 53, 58,
72, 78, 94, 104, 114, 124,
130, 142, 157, 165, 174,
183, 190, 195, 198, 204,
208
Power supply (24 pins)
These 24 V
DD
pins supply a voltage of +5 V
±
5% to the chip.
GND
1, 2, 8, 14, 21, 26, 31, 33,
40, 51, 52, 59, 73, 79, 91,
93, 105 ,106, 115, 123,
131, 141, 150, 155, 156,
166, 175, 182, 191, 196,
199, 205
Ground (32 pins)
Connect these pins to ground.
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