參數(shù)資料
型號(hào)： UPD98401A
廠商： NEC Corp.
英文描述： ATM SAR CHIP
中文描述： 自動(dòng)柜員機(jī)特區(qū)芯片
文件頁(yè)數(shù)： 1/36頁(yè)
文件大?。?/td> 216K
代理商： UPD98401A
The information in this document is subject to change without notice.
MOS INTEGRATED CIRCUIT
μ
PD98401A
ATM SAR CHIP
1997
Document No. S12100EJ3V0DS00 (3rd edition)
Date Published February 1999 N CP(K)
Printed in Japan
DATA SHEET
The mark
shows major revised points.
DESCRIPTION
The
μ
PD98401A (NEASCOT-S15
TM
) is a high-performance SAR chip that segments and reassembles ATM cells.
This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,
network hub, or router. The
μ
PD98401A conforms to the ATM Forum Recommendation, and provides the functions
of the AAL-5 SAR sublayer and ATM layer.
The
μ
PD98401A is compatible with its predecessor,
μ
PD98401, in terms of hardware and software.
Functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your
system.
μ
PD98401A User’s Manual: S12054E
FEATURES
Conforms to ATM Forum
AAL-5 SAR sublayer and ATM layer functions
Hardware support of AAL-5 processing
Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function
Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic
Supports up to 32K virtual channels (VC)
Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to
set different transmission rate for each VC
Interface and commands for controlling PHY device
Employs “UTOPIA interface” as cell data interface with PHY device
- Octet-level handshake
- Cell-level handshake
32-bit general-purpose bus interface
High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)
JTAG boundary scan test function (IEEE1149.1)
CMOS technology
+5 V single power source
Remark
In this document, an active low pin is indicated by
×××
_B (_B after a pin name).
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