參數(shù)資料
型號(hào)： UPD98401A
廠商： NEC Corp.
英文描述： ATM SAR CHIP
中文描述： 自動(dòng)柜員機(jī)特區(qū)芯片
文件頁(yè)數(shù)： 13/36頁(yè)
文件大小： 216K
代理商： UPD98401A
Data Sheet S12100EJ3V0DS00
13
μ
PD98401A
1.4 Control Memory Interface Pins
These pins constitute an interface through which the
μ
PD98401A accesses an external control memory and a
PHY device. A 18-bit address bus and a 32-bit data bus are used. The control memory of the host is accessed only
via this interface.
Pin Name
Pin No.
I/O
I/O Level
Function
CD31-CD28
CD27-CD21
CD20-CD16
CD15-CD7
CD6-CD0
110-113
116-122
125-129
132-140
143-149
I/O
3-state
TTL in,
CMOS out
Control Memory Data.
CD31 through CD0 are 3-state I/O pins and constitute a 32-bit data
bus which is used to transfer data with the control memory or a PHY
device.
CPAR3-
CPAR0
151-154
I/O
TTL in,
CMOS out
Control Memory Parity.
CPAR3 through CPAR0 indicate the parity of CD31 through CD0 in 8-
bit units. In the read cycle, the
μ
PD98401A checks the parity (when
enabled). In the write cycle, CPAR3 through CPAR0 output the parity.
Pull up these pins when they are not used.
CA17-C11
CA10-CA4
CA3-CA0
158-164
167-173
176-179
O
CMOS
Control Memory Address.
CA17 through CA0 constitute an 18-bit address bus. They output an
address to the control memory or a PHY device during read/write
operation.
CWE_B
186
O
CMOS
Control Memory Write Enable.
CWE_B signal indicates the direction in which the control memory is
accessed.
1: Read access
2: Write access
COE_B
187
O
CMOS
Control Memory Output Enable
COE_B enables or disables data output of the control memory.
CBE_B3
CBE_B2
CBE_B1
CBE_B0
180
181
184
185
O
CMOS
Local Port Byte Enable.
CBE_B3 through CBE_B0 indicate the byte on the control port to be
read or written.
INITD
188
I
TTL
Initialization Disable.
The INITD signal is used to disable automatic initialization of the
control memory during chip test. During normal operation other than
test, directly connect INITD to GND.
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