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參數(shù)資料
| 型號(hào)： | UPD98401A |
| 廠商： | NEC Corp. |
| 英文描述： | ATM SAR CHIP |
| 中文描述： | 自動(dòng)柜員機(jī)特區(qū)芯片 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 216K |
| 代理商： | UPD98401A |
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Data Sheet S12100EJ3V0DS00
11
μ
PD98401A
(3/3)
Pin Name
Pin No.
I/O
I/O Level
Function
SR/W_B
68
I
TTL
Slave Read/Write.
The SR/W_B signal determines the direction in which the slave is
accessed.
1: Read access
2: Write access
SEL_B
69
I
TTL
Slave Select.
This signal goes low (active) when the
μ
PD98401A is accessed as a
slave. The SEL_B signal must goes low as soon as or after the
ASEL_B signal has gone low. An inactive period of at least 2 system
clock cycles must be inserted between when the SEL_B signal has
become inactive and when it becomes active again.
ASEL_B
70
I
TTL
Slave Address Select.
The ASEL_B signal is used to select the direct address register of the
μ
PD98401A.
When a low level is input to ASEL_B, the
μ
PD98401A samples the AD
bus at the first rising edge of CLK.
CLK
32
I
TTL
Clock.
This pin inputs the system clock. Input a clock in a range of 8 to 33
MHz.
RST_B
29
I
TTL
Reset.
The RST_B signal initializes the
μ
PD98401A (on starting, etc.). After
reset, the
μ
PD98401A can start normal operation. When a low level is
input to RST_B, the internal state machine and registers of the
μ
PD98401A are reset, and all 3-state signals go into a high-
impedance state. The reset input is asynchronous. When this signal
is input during operation, the operating status at that time is lost. Hold
RST_B low at least for the duration of one clock. After reset, do not
access the
μ
PD98401A for at least 20 clock cycles.
INTR_B
71
O
Nch open-
drain output
Interrupt.
This is an open-drain signal and must be pulled up.
INTR_B informs the CPU that the interrupt bit (unmasked) of the GSR
register is set.
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