參數(shù)資料
型號(hào)： UPD780023AYCW(A)-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù)： 89/92頁
文件大小： 689K
代理商： UPD780023AYCW(A)-XXX
9
PD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)
Data Sheet U15131EJ3V0DS
OVERVIEW OF FUNCTIONS (1/2)
Part Number
PD780021A(A)
PD780022A(A)
PD780023A(A)
PD780024A(A)
Item
PD780021AY(A)
PD780022AY(A)
PD780023AY(A)
PD780024AY(A)
Internal
ROM
8 KB
16 KB
24 KB
32 KB
memory
High-speed RAM
512 bytes
1024 bytes
Memory space
64 KB
General-purpose registers
8 bits
× 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
On-chip minimum instruction execution time cycle variable function
When main system
Expanded-specification products of
PD780021A(A), 780022A(A), 780023A(A), 780024A(A):
clock selected
0.166
s/0.333 s/0.666 s/1.33 s/2.66 s (@12 MHz, VDD = 4.5 to 5.5 V operation)
PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A) and conventional products
of
PD780021A(A), 780022A(A), 780023A(A), 780024A(A):
0.238
s/0.48 s/0.95 s/1.91 s/3.81 s (@8.38 MHz, VDD = 4.0 to 5.5 V operation)
When subsystem
122
s (@ 32.768 kHz operation)
clock selected
Instruction set
16-bit operation
Multiply/divide (8 bits
× 8 bits,16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjust, etc.
I/O ports
Total:
51
CMOS input:
8
CMOS I/O:
39
N-ch open-drain I/O (5 V withstanding voltage): 4
A/D converter
8-bit resolution
× 8 channels
Low-voltage operation available: AVDD = 1.8 to 5.5 V
Serial interface
PD780021A(A), 780022A(A), 780023A(A), 780024A(A)
UART mode:
1 channel
3-wire serial I/O mode: 2 channels
PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)
UART mode:
1 channel
3-wire serial I/O mode:
1 channel
I2C bus mode (multimaster supporting): 1 channel
Timers
16-bit timer/event counter: 1 channel
8-bit timer/event counter:
2 channels
Watch timer:
1 channel
Watchdog timer:
1 channel
Timer outputs
3 (8-bit PWM output capable: 2)
time
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