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參數(shù)資料
| 型號： | UPD780023AYCW(A)-XXX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, PLASTIC, SDIP-64 |
| 文件頁數(shù)： | 66/92頁 |
| 文件大小： | 689K |
| 代理商： | UPD780023AYCW(A)-XXX |
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69
PD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)
Data Sheet U15131EJ3V0DS
(f) I2C bus mode (
PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A) only)
Parameter
Symbol
Standard Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
fCLK
0
100
0
400
kHZ
Bus free time
tBUF
4.7
—
1.3
—
s
(between stop and start conditions)
Hold timeNote 1
tHD:STA
4.0
—
0.6
—
s
SCL0 clock low-level width
tLOW
4.7
—
1.3
—
s
SCL0 clock high-level width
tHIGH
4.0
—
0.6
—
s
Start/restart condition setup time
tSU:STA
4.7
—
0.6
—
s
Data hold time CBUS-compatible master
tHD:DAT
5.0
—
——
s
I2C bus
0Note 2
—
0Note 2
0.9Note 3
s
Data setup time
tSU:DAT
250
—
100Note 4
—
ns
SDA0 and SCL0 signal rise time
tR
—
1000
20 + 0.1CbNote 5
300
ns
SDA0 and SCL0 signal fall time
tF
—
300
20 + 0.1CbNote 5
300
ns
Stop condition setup time
tSU:STO
4.0
—
0.6
—
s
Spike pulse width controlled by input filter
tSP
—
0
50
ns
Capacitive load per bus line
Cb
—
400
—
400
pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).
3. If the device does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time
tHD:DAT needs to be fulfilled.
4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions
described below must be satisfied.
If the device does not extend the SCL0 signal low state hold time
tSU:DAT
≥ 250 ns
If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1000 + 250 = 1250 ns by standard mode I2C bus specification).
5. Cb: Total capacitance per bus line (unit: pF)
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