參數(shù)資料
型號(hào)： UPD780023AYCW(A)-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù)： 16/92頁
文件大?。?/td> 689K
代理商： UPD780023AYCW(A)-XXX
23
PD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)
Data Sheet U15131EJ3V0DS
5.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
Expanded-specification products of
PD780021A(A), 780022A(A), 780023A(A), 780024A(A)
0.166
s/0.333 s/0.666 s/1.33 s/2.66 s
(@12 MHz, VDD = 4.5 to 5.5 V operation with main system clock)
122
s (@32.768 kHz, VDD = 4.0 to 5.5 V operation with subsystem clock)
PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A), and conventional products of PD780021A(A),
780022A(A), 780023A(A), 780024A(A)
0.238
s/0.48 s/0.95 s/1.91 s/3.81 s (@8.38 MHz, VDD = 4.0 to 5.5 V operation with main system clock)
122
s (@32.768 kHz, VDD = 4.0 to 5.5 V operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1
XT2
X1
X2
fXT
fX
Subsystem
clock
oscillator
Watch timer, clock
output function
Prescaler
Main system
clock
oscillator
Clock to peripheral
hardware
CPU clock
(fCPU)
Standby
controller
Wait
controller
2
fX
22
fX
23
fX
24
fX
fXT
2
Prescaler
Selector
STOP
2
1
HALT
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