參數(shù)資料
型號： UPD780023AYCW(A)-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù)： 21/92頁
文件大小： 689K
代理商： UPD780023AYCW(A)-XXX
28
PD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)
Data Sheet U15131EJ3V0DS
5.4 Clock Output/Buzzer Output Controller
A clock output/buzzer output controller is incorporated.
Clocks with the following frequencies can be output as clock output.
Expanded-specification products of
PD780021A(A), 780022A(A), 780023A(A), 780024A(A)
93.75 kHz/187.5 kHz/375 kHz/750 kHz/1.25 MHz/3 MHz/6 MHz/12 MHz (@12 MHz operation with main
system clock)
32.768 kHz (@32.768 kHz operation with subsystem clock)
PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A), and conventional products of
PD780021A(A), 780022A(A), 780023A(A), 780024A(A)
65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@8.38 MHz operation with
main system clock)
32.768 kHz (@32.768 kHz operation with subsystem clock)
Clocks with the following frequencies can be output as buzzer output.
Expanded-specification products of
PD780021A(A), 780022A(A), 780023A(A), 780024A(A)
1.46 kHz/2.93 kHz/5.86 kHz/11.7 kHz (@12 MHz operation with main system clock)
PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A), and conventional products of
PD780021A(A), 780022A(A), 780023A(A), 780024A(A)
1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@8.38 MHz operation with subsystem clock)
Figure 5-7. Block Diagram of Clock Output/Buzzer Output Control Circuit
Prescaler
fX
fXT
8
Clock
controller
PCL/P74
BUZ/P75
4
fX to fX/27
fX/210 to fX/213
Selector
BCS0, BCS1
BZOE
CLOE
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Internal bus
Clock output selection register (CKS)
Selector
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