參數(shù)資料
型號: UPD750066CU(A)-XXX
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-42
文件頁數(shù): 9/83頁
文件大?。?/td> 730K
代理商: UPD750066CU(A)-XXX
17
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V1DS
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure
4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 100
×BNote at the beginning of a program. When using
the Mk II mode, it must be initialized to 000
×BNote.
Note
Set the desired value in the
× position.
Figure 4-1. Stack Bank Select Register Format
SBS3
SBS2
SBS1
SBS0
3210
Symbol
SBS
Address
F84H
00
01
0
1
0
Memory bank 0
Memory bank 1
Other than above setting prohibited
0 must be set in the bit 2 position.
Stack area specification
Mk II mode
Mk I mode
Mode switching specification
Caution
Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode.
When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode.
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