參數(shù)資料
型號(hào)： UPD750066CU(A)-XXX
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-42
文件頁數(shù)： 49/83頁
文件大小： 730K
代理商： UPD750066CU(A)-XXX
53
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V1DS
Instruction
Number
Addressing
Mnemonic
Operand
of Machine
Operation
Skip Condition
Group
of Bytes
Cycles
Area
Subroutine
RETINote 1
13
PD750064
stack control
MBE, RBE, 0, 0
← (SP+1)
PC11–0
← (SP) (SP+3) (SP+2)
PSW
← (SP+4) (SP+5), SP ← SP+6
PD750066, 750068
MBE, RBE, 0, PC12
← (SP+1)
PC11–0
← (SP) (SP+3) (SP+2)
PSW
← (SP+4) (SP+5), SP ← SP+6
PD750064
0, 0, 0, 0
← (SP+1)
PC11–0
← (SP) (SP+3) (SP+2)
PSW
← (SP+4) (SP+5), SP ← SP+6
PD750066, 750068
0, 0, 0, PC12
← (SP+1)
PC11–0
← (SP) (SP+3) (SP+2)
PSW
← (SP+4) (SP+5), SP ← SP+6
PUSH
rp
1
(SP–1)(SP–2)
← rp, SP ← SP–2
BS
2
(SP–1)
← MBS, (SP–2) ← RBS, SP ← SP–2
POP
rp
1
rp
← (SP+1) (SP), SP ← SP+2
BS
2
MBS
← (SP+1), RBS ← (SP), SP ← SP+2
Interrupt
EI
2
IME (IPS.3)
← 1
control
IE
×××
22
IE
××× ← 1
DI
2
IME (IPS.3)
← 0
IE
×××
22
IE
××× ← 0
Input/output
INNote 2
A, PORTn
2
A
← PORTn
(n = 0-6, 11)
XA, PORTn
2
XA
← PORTn+1, PORTn
(n = 4)
OUTNote 2
PORTn, A
2
PORTn
← A
(n = 2-6)
PORTn, XA
2
PORTn+1, PORTn
← XA
(n = 4)
CPU control
HALT
2
Set HALT Mode (PCC.2
← 1)
STOP
2
Set STOP Mode (PCC.3
← 1)
NOP
1
No Operation
Special
SEL
RBn
2
RBS
← n
(n = 0-3)
MBn
2
MBS
← n
(n = 0, 1, 15)
Notes 1.
The operations indicated with thick lines can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
2.
While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and
MBS must be set to 15.
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