參數(shù)資料
型號(hào)： UPD750066CU(A)-XXX
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-42
文件頁(yè)數(shù)： 59/83頁(yè)
文件大?。?/td> 730K
代理商： UPD750066CU(A)-XXX
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
62
Data Sheet U10165EJ2V1DS
Note 2
Serial transfer operation
2-wire and 3-wire serial I/O modes (SCK internal clock output): (TA = –40 to +85C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY1
VDD = 2.7 to 5.5 V
1300
ns
3800
ns
SCK high-/low-level width
tKL1,VDD = 2.7 to 5.5 V
tKCY1/2–50
ns
tKH1
tKCY1/2–150
ns
SINote 1 setup time (to SCK
↑)tSIK1
VDD = 2.7 to 5.5 V
150
ns
500
ns
SINote 1 hold time
tKSI1
VDD = 2.7 to 5.5 V
400
ns
(from SCK
↑)
600
ns
SCK
↓ → SONote 1 output
tKSO1
RL = 1 k
,VDD = 2.7 to 5.5 V
0
250
ns
delay time
CL = 100 pF
0
1000
ns
Notes 1.
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
2.
RL and CL are the load resistance and load capacitance of the SO output line.
2-wire and 3-wire serial I/O modes (SCK external clock input): (TA = –40 to +85C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY2
VDD = 2.7 to 5.5 V
800
ns
3200
ns
SCK high-/low-level width
tKL2,VDD = 2.7 to 5.5 V
400
ns
tKH2
1600
ns
SINote 1 setup time (to SCK
↑)tSIK2
VDD = 2.7 to 5.5 V
100
ns
150
ns
SINote 1 hold time
tKSI2
VDD = 2.7 to 5.5 V
400
ns
(from SCK
↑)
600
ns
SCK
↓ → SONote 1 output
tKSO2
RL = 1 k
,VDD = 2.7 to 5.5 V
0
300
ns
delay time
CL = 100 pF
0
1000
ns
Notes 1.
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
2.
RL and CL are the load resistance and load capacitance of the SO output line.
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