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參數(shù)資料
| 型號(hào)： | UPD750066CU(A)-XXX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-42 |
| 文件頁數(shù)： | 33/83頁 |
| 文件大?。?/td> | 730K |
| 代理商： | UPD750066CU(A)-XXX |
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V1DS
Table 9-1. Status of Each Hardware After Reset (1/2)
Hardware
RESET Signal Generation
in Standby Mode
in Operation
Program counter (PC)
PD750064 Sets the low-order 4 bits of
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11 to PC8 and
the contents of address 0001H
to the PC7 to PC0.
PD750066, Sets the low-order 5 bits of
Sets the low-order 5 bits of
750068
program memory’s address
0000H to the PC12 to PC8 and
the contents of address 0001H
to the PC7 to PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0 to SK2)
0
Interrupt status flag (IST0, IST1)
0
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Stack bank select register (SBS)
1000B
Data memory (RAM)
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
Basic interval
Counter (BT)
Undefined
timer/watchdog
Mode register (BTM)
0
timer
Watchdog timer enable flag (WDTM)
00
Timer/event
Counter (T0)
0
counter (T0)
Modulo register (TMOD0)
FFH
Mode register (TM0)
0
TOE0, TOUT F/F
0, 0
Timer/event
Counter (T1)
0
counter (T1)
Modulo register (TMOD1)
FFH
Mode register (TM1)
0
TOE1, TOUT F/F
0, 0
Watch timer
Mode register (WM)
0
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