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CHAPTER 14 A/D CONVERTER
User’s Manual U16890EJ1V0UD
422
14.4.2 A/D conversion operation
Setting the ADM.ADCS bit to 1 starts conversion of the signal input to the channel specified by the ADS register.
Upon completion of the conversion, the conversion result is stored in the ADCR register and a new conversion
starts.
If the ADM, ADS, PFT, or PFM register is written during conversion, conversion is interrupted and the
conversion operation starts again from the beginning.
If the ADCS bit is cleared to 0 during conversion, conversion is interrupted and the conversion operation is
stopped.
For whether or not the conversion end interrupt request signal (INTAD) is generated, refer to
14.4.3
.
14.4.3 Power fail monitoring function
The conversion end interrupt request signal (INTAD) can be controlled as follows using the PFM and PFT registers.
If the PFM.PFEN bit = 0, the INTAD signal is generated each time conversion ends.
If the PFEN bit = 1 and the PFM.PFCM bit = 0, the conversion result and the value of the PFT register are
compared when conversion ends, and the INTAD signal is output only if ADCRH
≥
PFT.
If the PFEN and PFCM bits = 1, the conversion result and the value of the PFT register are compared when
conversion ends and the INTAD signal is output only if ADCRH < PFT.
Because, when the PFEN bit = 1, the conversion result is overwritten after the INTAD signal has been output,
unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the
actual operation differs from the operation described above (refer to
Figure 14-4
).
Figure 14-4. Power Fail Monitoring Function (PFCM Bit = 0)
Conversion operation
ADCRH
PFT
INTAD
ANI0
80H
80H
7FH
80H
ANI0
ANI0
ANI0
Note
Note
If reading is not performed during this interval, the conversion result changes to the next conversion result.