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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16890EJ1V0UD
256
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TP0CCRa register
To change the set value of the TP0CCRa register to a smaller value, stop counting once, and then change
the set value.
If the value of the TP0CCRa register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TP0CE bit
TP0CCR0 register
INTTP0CC0 signal
TP0CCR1 register
INTTP0CC1 signal
TOP01 pin output
External trigger input
(TIP00 pin input)
D
10
D
11
D
00
D
01
D
00
D
10
D
10
D
10
D
01
D
11
D
00
D
00
Delay
(D
10
)
Active level width
(D
00
D
10
+ 1)
Delay
(D
10
)
Active level width
(D
00
D
10
+ 1)
Delay
(10000H + D
11
)
Active level width
(D
01
D
11
+ 1)
TOP00 pin output
(software trigger)
When the TP0CCR0 register is rewritten from D
00
to D
01
and the TP0CCR1 register from D
10
to D
11
where
D
00
> D
01
and D
10
> D
11
, if the TP0CCR1 register is rewritten when the count value of the 16-bit counter is
greater than D
11
and less than D
10
and if the TP0CCR0 register is rewritten when the count value is greater
than D
01
and less than D
00
, each set value is reflected as soon as the register has been rewritten and
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
11
, the counter generates the INTTP0CC1 signal and asserts the TOP01
pin. When the count value matches D
01
, the counter generates the INTTP0CC0 signal, deasserts the
TOP01 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
a = 0, 1