
CHAPTER 10 8-BIT TIMER H
User’s Manual U16890EJ1V0UD
374
Figure 10-5. Operation Timing in PWM Output Mode (4/4)
Operation based on CMPn1 transitions (CMPn1 = 01H
→
03H, CMPn0 = A5H)
Count clock
CMPn0
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
00H
01H 02H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
<1>
<4>
<3>
<2>
CMPn1
<6>
<5>
01H
A5H
03H
01H (03H)
<2>'
8-bit timer counter
Hn count value
<1> When the TMHEn bit is set to 1, counting starts. At this time, the TOHn output remains inactive (TOLEVn
bit = 0).
<2> The set value of the CMPn1 register can be changed during count operation. This operation is
asynchronous to the count clock.
<3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer
counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is generated.
<4> Even if the value of the CMPn1 register is changed, that value is latched and not transferred to the
register. When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register prior to
the change match, the changed value is transferred to the CMPn1 register and the value of the CMPn1
register is changed (<2>’).
However, three or more count clocks are required from the time the value of the CMPn1 register is
changed until it is transferred to the register. Even if a match signal is generated within three count
clocks, the changed value cannot be transferred to the register.
<5> When the count value of 8-bit timer counter Hn matches the changed set value of the CMPn1 register,
the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not
generated.
<6> When the TMHEn bit is cleared to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn
output become inactive.