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CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U14492EJ5V0UD
419
(4) Receive buffer register 0 (RXB0)
The RXB0 register is an 8-bit buffer register for storing parallel data that had been converted by the receive
shift register.
When reception is enabled (RXE0 bit = 1 in the ASIM0 register), receive data is transferred from the receive
shift register to the RXB0 register, synchronized with the completion of the shift-in processing of one frame.
Also, a reception completion interrupt request (INTSR0) is generated by the transfer to the RXB0 register.
For information about the timing for generating this interrupt request, refer to
10.2.5 (4) Reception
operation
.
If reception is disabled (RXE0 bit = 0 in the ASIM0 register), the contents of the RXB0 register are retained,
and no processing is performed for transferring data to the RXB0 register even when the shift-in processing
of one frame is completed. Also, no INTSR0 signal is generated.
When 7 bits is specified for the data length, bits 6 to 0 of the RXB0 register are transferred for the receive
data and the MSB (bit 7) is always 0. However, if an overrun error (OVE bit of ASIS0 register = 1) occurs, the
receive data at that time is not transferred to the RXB0 register.
Except when a reset is input, the RXB0 register becomes FFH even when UARTCAE0 bit = 0 in the ASIM0
register.
This register is read-only, in 8-bit units.
7
6
5
4
3
2
1
0
Address
Initial value
RXB0
RXB7
RXB6
RXB5
RXB4
RXB3
RXB2
RXB1
RXB0
FFFFFA02H
FFH
Bit position
Bit name
Function
7 to 0
RXB7 to
RXB0
Stores receive data.
0 can be read for RXB7 when 7-bit or character data is received.