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CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U14492EJ5V0UD
423
(2) Transmission operation
When UARTCAE0 bit is set to 1 in the ASIM0 register, a high level is output from the TXD0 pin.
Then, when TXE0 bit is set to 1 in the ASIM0 register, transmission is enabled, and the transmit operation is
started by writing transmit data to transmit buffer register 0 (TXB0).
(a) Transmission enabled state
This state is set by the TXE0 bit in the ASIM0 register.
TXE0 = 1: Transmission enabled state
TXE0 = 0: Transmission disabled state
Since UART0 does not have a CTS (transmission enabled signal) input pin, a port should be used to
confirm whether the destination is in a reception enabled state.
(b) Transmission operation start
In transmission enabled state, a transmission operation is started by writing transmit data to transmit
buffer register 0 (TXB0). When a transmit operation is started, the data in the TXB0 register is
transferred to the transmit shift register. Then, the transmit shift register outputs data to the TXD0 pin
(the transmit data is transferred sequentially starting with the start bit). The start bit, parity bit, and stop
bits are added automatically.
(c) Transmission interrupt request
When the transmit shift register becomes empty, a transmission completion interrupt request (INTST0) is
generated. The timing for generating the INTST0 signal differs according to the specification of the stop
bit length. The INTST0 signal is generated at the same time that the last stop bit is output.
If the data to be transmitted next has not been written to the TXB0 register, the transmit operation is
suspended.
Caution Normally, when the transmit shift register becomes empty, a transmission completion
interrupt (INTST0) is generated. However, no INTST0 signal is generated if the transmit
shift register becomes empty due to the input of a RESET.