
CHAPTER 1 INTRODUCTION
24
User’s Manual U14492EJ5V0UD
1.5 Pin Configuration (Top View)
144-pin plastic LQFP (fine pitch) (20
×
20)
μ
PD703116GJ-xxx-UEN, 703116GJ-xxx-UEN-A, 703116GJ(A)-xxx-UEN, 703116GJ(A)-xxx-UEN-A,
μ
PD703116GJ(A1)-xxx-UEN, 703116GJ(A1)-xxx-UEN-A, 70F3116GJ-UEN, 70F3116GJ-UEN-A,
μ
PD70F3116GJ(A)-UEN, 70F3116GJ(A)-UEN-A, 70F3116GJ(A1)-UEN, 70F3116GJ(A1)-UEN-A
ANI07
AV
DD
AV
SS
AV
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ANI16
TRIANI17
AD3_DBG
AD2_DBG
AD1_DBG
AD0_DBG
CLSYNC
RESET
CV
DD
CV
SS
X1
X2
CKSEL
MODE0
MODE1
MODE2
SI0/P40
SO0/P41
SCK0/P42
SI1/P43
SO1/P44
SCK1/P45
CRXD/P46
CTXD/P47
TIUD11/TO11/P13
TCLR10/INTP101/P12
TCUD10/INTP100/P11
TIUD10/TO10/P10
PCM4
HLDRQ/PCM3
HLDAK/PCM2
CLKOUT/PCM1
WAIT/PCM0
PCT7
ASTB/PCT6
PCT5
RD/PCT4
PCT3
PCT2
UWR/PCT1
LWR/PCT0
V
DD5
SS5
V
CS7/PCS7
CS6/PCS6
CS5/PCS5
CS4/PCS4
CS3/PCS3
CS2/PCS2
CS1/PCS1
CS0/PCS0
A23/PDH7
A22/PDH6
A21/PDH5
A20/PDH4
A19/PDH3
A18/PDH2
A17/PDH1
A16/PDH0
R
T
R
T
A
R
T
A
T
T
T
T
T
T
T
T
V
D
V
S
V
S
V
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
R
A
S
A
D
T
T
T
T
T
T
V
D
V
S
V
S
V
D
T
T
T
T
T
T
I
I
I
A
A
E
E
N
N
T
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
7
7
7
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Note 1
Notes 1.
μ
PD70F3116 only
As follows in
μ
PD703116.
TRIG_DBG: IC1, AD0_DBG to AD3_DBG: IC2, SYNC: IC3, CLK_DBG: IC4
2.
μ
PD703116: IC5
μ
PD70F3116: V
PP
3.
The NMI/P00 pin always functions as the NMI pin. The NMI pin level can be read by reading the
P0.P00 bit.
Cautions 1. When using the
μ
PD70F3116 in normal mode, connect the V
PP
pin to V
SS5
.
2. When using the
μ
PD703116, the processing when the IC1 to IC5 pins are unused is as
follows.
IC1 to IC4 pins: Leave open.
IC5 pin: Independently connect to V
SS5
via a resistor.