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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
195
User’s Manual U14492EJ5V0UD
Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgement (Outline)
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgment operation
Instruction (start instruction of interrupt servicing routine)
Interrupt request
IF
ID
EX
DF
WB
IFX
IDX
4 system clocks
IF
Interleave
access
IF
ID
EX
INT1 INT2 INT3 INT4
IF
IFX
Note
For details of interleave access, refer to
8.1.2 2-clock branch
in
V850E1 Architecture User’s Manual
(U14559E)
.
Remark
INT1 to INT4: Interrupt acknowledgment processing
IFX:
Invalid instruction fetch
IDX:
Invalid instruction decode
Interrupt response time (internal system clock (f
XX
))
External interrupt
Internal
interrupt
INTP0 to INTP6,
INTP20 to INTP25
INTP20 to INTP25
INTP100, INTP101,
INTP110, INTP111
INTP30, INTP31
Condition
Minimum
4
4 +
analog delay time
4 +
digital noise filter
4 +
Note 1
+
digital noise filter
Maximum
7
Note 2
7 +
analog delay time
7 +
digital noise filter
7 +
Note 1
+
digital noise filter
The following cases are
exceptions.
In IDLE/software STOP
mode
External bus access
Two or more interrupt
request non-sampling
instructions are executed
in succession
Access to on-chip
peripheral I/O register
Access to programmable
peripheral I/O register
Notes 1.
The number of internal system clocks are as follows.
For timers 10, 11 (TM10, TM11) using INTP100, INTP101, INTP110, and INTP111 as external
interrupt inputs (see
9.2.4 (1) Timer 1/timer 2 clock selection register (PRM02)
):
f
CLK
= f
XX
/2 (PRM2 bit = 1): 2
f
CLK
= f
XX
/4 (PRM2 bit = 0): 4
For timer 3 (TM3) using INTP30 and INTP31 as external interrupt inputs (see
9.4.4 (1) Timer
3 clock selection register (PRM03)
):
f
CLK
= f
XX
(PRM3 bit = 1): 2
f
CLK
= f
XX
/2 (PRM3 bit = 0): 4
2.
When LD instruction is executed to internal ROM (during align access)