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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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User’s Manual U14492EJ5V0UD
7.8 Periods in Which CPU Does Not Acknowledge Interrupts
The CPU acknowledges an interrupt while an instruction is being executed. However, no interrupt will be
acknowledged between an interrupt request non-sampling instruction and the next instruction (interrupt is held
pending).
The interrupt request non-sampling instructions are as follows.
EI instruction
DI instruction
LDSR reg2, 0x5 instruction (for PSW)
The store instruction for the command register (PRCMD)
The store instructions or bit manipulation instructions of SET1, CLR1, and NOT1 instructions for the following
registers:
Interrupt-related registers:
Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3)
Power save control register (PSC)
CSI-related registers:
Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1)
Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1)
Clocked serial interface receive buffer registers 0, 1 (SIRB0, SIRB1)
Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1)
Clocked serial interface transmit buffer registers 0, 1 (SOTB0, SOTB1)
Clocked serial interface transmit buffer registers L0, L1 (SOTBL0, SOTBL1)
Clocked serial interface read-only receive buffer registers 0, 1 (SIRBE0, SIRBE1)
Clocked serial interface read-only receive buffer registers L0, L1 (SIRBEL0, SIRBEL1)
Clocked serial interface initial transmit buffer registers 0, 1 (SOTBF0, SOTBF1)
Clocked serial interface initial transmit buffer registers L0, L1 (SOTBFL0, SOTBFL1)
Serial I/O shift registers 0, 1 (SIO0, SIO1)
Serial I/O shift registers L0, L1 (SIOL0, SIOL1)
Prescaler mode register (PRSM3)
Prescaler compare register (PRSCM3)
FCAN clock selection register (PRM04)
Remark
xx: Identification name of each peripheral unit (refer to
Table 7-2
)
n: Peripheral unit number (refer to
Table 7-2
)