參數資料
型號: TVP5160PNPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉換
英文描述: COLOR SIGNAL DECODER, PQFP128
封裝: PLASTIC, HTQFP-128
文件頁數: 91/119頁
文件大?。?/td> 1347K
代理商: TVP5160PNPG4
Internal Control Registers
63
February 2005 Revised April 2006
SLES135A
4.1.61
SDRAM Control
Subaddress
59h
Default
00h
7
6
5
4
3
2
1
0
Reserved
SDRAM_CLK delay control
Enable
Configuration[1:0]
Bit 1 Bit 0
Arrangement
0
2 banks x 2048 rows x 256 columns
16 Mbits
0
1
4 banks x 2048 rows x 256 columns
32 Mbits
1
0
2 banks x 4096 rows x 256 columns
32 Mbits
1
4 banks x 4096 rows x 256 columns
64 Mbits
Memories with more rows, columns, and/or banks can be used as long as the minimum requirements are met.
Additional rows, columns, and/or banks are ignored and unused by the memory controller.
The memory controller must be configured before enabling 3DYC or 3DNR; otherwise, incorrect operation of
the memory controller will result.
Enable:
0 = SDRAM controller disabled (default)
1 = SDRAM controller enabled
SDRAM_CLK delay control[3:0]
This register changes the delay from the default position of SDRAM_CLK in increments of approximately
0.58 ns
Bit 3 Bit 2 Bit 1 Bit 0
Delay
0
0 (default)
0
1
0.58 ns
1
0
1.16 ns
LL
L
1
9.3 ns
4.1.62
3DNR Y Noise Sensitivity
Subaddress
5Ah
Default
80h
7
6
5
4
3
2
1
0
Y noise sensitivity[7:0]
4.1.63
3DNR UV Noise Sensitivity
Subaddress
5Bh
Default
80h
7
6
5
4
3
2
1
0
UV noise sensitivity[7:0]
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