參數(shù)資料
型號： TVP5160PNPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： PLASTIC, HTQFP-128
文件頁數(shù)： 31/119頁
文件大小： 1347K
代理商： TVP5160PNPG4
Introduction
9
February 2005 Revised April 2006
SLES135A
Table 21. Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
I/O
DESCRIPTION
Host Interface
SDA
31
I/O
I2C data bus
SCL
30
I
I2C clock input
Power Supplies
A33GND
1, 26, 27,
28, 126, 128
P
Analog 3.3-V return. Connect to analog ground.
A33VDD
2, 25, 125
P
Analog power. Connect to analog 3.3-V supply.
A18GND
12, 14, 15
P
Analog 1.8-V return. Connect to analog ground.
A18VDD
11, 13, 16
P
Analog power. Connect to analog 1.8-V supply.
PLL18GND
124
P
Analog power return. Connect to analog ground.
PLL18VDD
123
P
Analog power. Connect to analog 1.8-V supply.
DGND
29, 34, 48,
66, 86, 100,
112, 120
P
Digital return. Connect to digital ground.
DVDD
33, 47, 65,
85, 99, 111
P
Digital core power. Connect to 1.8-V supply.
IOGND
38, 58, 75,
93, 106
P
Digital power return. Connect to digital ground.
IOVDD
37, 57, 74,
92, 105
P
Digital I/O power. Connect to digital 3.3-V supply.
Sync Signals
HS / CS / GPIO
117
I/O
Horizontal sync output or digital composite sync output
Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
VS / VBLK /
GPIO
118
I/O
Vertical sync output. (for modes with dedicated VS) or vertical blanking output
Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
FID / GPIO
116
I/O
Odd/even field indicator
Programmable general purpose I/O
This pin must be pulled low through a 10-k resistor for correct device operation.
AVID / GPIO
115
I/O
Active video indicator
Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
SDRAM Interface
Address[11:0]
61, 77,
6264,
6769,
8178
O
SDRAM address bus
D[15:0]
4956,
4639
I/O
SDRAM data bus
WE
70
O
SDRAM write enable
CAS
71
O
SDRAM CAS enable
RAS
72
O
SDRAM RAS enable
DQM
59
O
SDRAM input/output mask for data
BA[1:0]
76, 73
O
SDRAM bank address
SDRAM_CLK
60
O
SDRAM 108-MHz clock
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