參數(shù)資料
型號： TVP5160PNPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： PLASTIC, HTQFP-128
文件頁數(shù)： 62/119頁
文件大?。?/td> 1347K
代理商： TVP5160PNPG4
Internal Control Registers
37
February 2005 Revised April 2006
SLES135A
4.1.6 Color Killer
Subaddress
05h
Default
10h
7
6
5
4
3
2
1
0
Reserved
Automatic color killer
Color killer threshold [4:0]
Automatic color killer:
00 = Automatic mode (default)
01 = Reserved
10 = Color killer enabled, the UV terminals are forced to a zero color state
11 = Color killer disabled
Color killer threshold [4:0]:
11111 = 31 (maximum)
10000 = 16 (default)
00000 = 0 (minimum)
4.1.7 Luminance Processing Control 1
Subaddress
06h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Pedestal
Reserved
VBI raw
Reserved
Luminance signal delay [2:0]
Pedestal:
0 = 7.5 IRE pedestal is present on the analog video input signal (default)
1 = Pedestal is not present on the analog video input signal
VBI raw:
0 = Disable (default)
1 = Enable
During the duration of the vertical blanking as defined by VBLK start and stop registers 22h through 25h, the
chroma samples are replaced by luma samples. This feature may be used to support VBI processing
performed by an external device during the vertical blanking interval. In order to use this bit, the output format
must be the 10-bit, ITU-R BT.656 mode.
Luminance signal delay [2:0]: Luminance signal delays respect to chroma signal in 1x pixel clock increments.
011 = 3 pixel clocks delay
010 = 2 pixel clocks delay
001 = 1 pixel clock delay
000 = 0 pixel clock delay (default)
111 = 1 pixel clock delay
110 = 2 pixel clocks delay
101 = 3 pixel clocks delay
100 = 0 pixel clock delay
相關(guān)PDF資料
PDF描述
TVP5160PNP COLOR SIGNAL DECODER, PQFP128
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TVP6000CPFP COLOR SIGNAL ENCODER, PQFP80
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TVP7000PZPRG4 SPECIALTY CONSUMER CIRCUIT, PQFP100
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