參數(shù)資料
型號(hào): TVP5160PNPG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP128
封裝: PLASTIC, HTQFP-128
文件頁(yè)數(shù): 47/119頁(yè)
文件大?。?/td> 1347K
代理商: TVP5160PNPG4
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Functional Description
23
February 2005 Revised April 2006
SLES135A
3.8
Embedded Syncs
Standard with embedded syncs insert SAV and EAV codes into the data stream on the rising and falling edges
of AVID. These codes contain the V and F bits which also define vertical timing. Table 35 gives the format
of the SAV and EAV codes.
H equals 1b always indicates EAV. H equals 0b always indicates SAV. The alignment of V and F to the line
and field counter varies depending on the standard.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 35. EAV and SAV Sequence
Y9 (MSB)
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Preamble
1
Preamble
0
Preamble
0
Status
1
F
V
H
P3
P2
P1
P0
0
3.9
I2C Host Interface
Communication with the TVP5160 decoder is via an I2C host interface. The I2C standard consists of two
signals, the serial input/output data (SDA) line and input/output clock line (SCL), which carry information
between the devices connected to the bus. A 2-bit control signal (I2CA0/ I2CA1) selects the slave address.
Although an I2C system can be multi-mastered, the TVP5160 decoder can function as a slave device only.
Since SDA and SCL are kept open-drain at logic high output level or when the bus is not driven, the user must
connect SDA and SCL to IOVDD via a pullup resistor on the board. The slave address select, terminals 83
and 82 (I2CA0 and I2CA1), enables the use of four TVP5160 devices tied to the same I2C bus since it controls
the two least significant bits of the I2C device address.
Table 36. I2C Host Interface Terminal Description
SIGNAL
TYPE
DESCRIPTION
I2CA0
I
Slave address selection
I2CA1
I
Slave address selection
SCL
I/O
Input clock line
SDA
I/O
Input/output data line
3.9.1 Reset and I2C Bus Address Selection
The TVP5160 decoder can respond to four possible chip addresses. The address selection is made at reset
by an externally supplied level on the I2CA0/ I2CA1 pins. The TVP5160 decoder samples the level of terminals
83 and 82 at power up or at the trailing edge of RESETB and configures the I2C bus address bit A0/A1. The
I2CA0 and I2CA1 terminals have internal pulldown resistors to pull the terminals low to set a 0b.
Table 37. I2C Host Interface Device Addresses
A6
A5
A4
A3
A2
A1(I2CA1)
A0 (I2CA0)
R/W
HEX
1
0
1
0 (default)
1/0
B9/B8
1
0
1
0
1
1/0
BB/BA
1
0
1
0
1/0
BD/BC
1
0
1
1/0
BF/BE
NOTE: To pull up the I2C terminals high, tie to IOVDD via a 2.2-k resistor.
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