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參數(shù)資料
| 型號： | TPU3035PK |
| 元件分類： | 圖文 |
| 英文描述： | TELETEXT DECODER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 71/72頁 |
| 文件大?。?/td> | 347K |
| 代理商： | TPU3035PK |
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PRELIMINARY DATA SHEET
TPU 3035, TPU 3040, TPU 3050
8
Micronas
Level 1 Buffer
Level 2 Buffer
Pointer
1
0
1
0
1
0
Char 3 Attr.
Char 6 Attr.
0
1
Char 10 Attr.
1
0
1
Char 36 Attr.
Char 3 Attr.
Char 6 Attr.
Char 10 Attr.
Char 1
Char 2
Char 3
Char 4
Char 5
Char 6
Char 7
Char 8
Char 9
Char 10
Char 36
Char 37
Char 38
Char 39
Char 40
Fig. 2–2: Stack Row Buffer
1
2.5. WST Display Controller
The display controller includes two row buffers. The first
row buffer holds a copy of a teletext row from the display
page buffer. This decreases the data rate through the
DRAM interface by a factor of 10 or 8, because new tele-
text row data is needed only after 10 lines in PAL or 8
lines in NTSC mode. The second row buffer stores all
display attributes in parallel, to allow level 2 display with-
out additional decoding.
To present a WST level 2 display, the teletext display
controller has to evaluate the following attributes in par-
allel, that is for every character location:
– 10-bit character code
– 5-bit foreground color
– 5-bit background color
– 2-bit size
– 5-bit flash
– 1-bit invert
– 1-bit separated
– 1-bit conceal
– 1-bit underline
– 1-bit boxing/window
Additional attributes are defined to improve the display
of CAPTION and OSD text:
– 1-bit italics
– 1-bit shadow
The display controller delivers 5-bit digital color informa-
tion, a shadow signal for contrast reduction and a fast
blank signal. The color bus can be used to address ex-
ternal color-look-up-tables (CLUT) which are part of
modern digital TV systems, such as the DIGIT 3000. By
this means, the full level 2 color spectrum can be dis-
played. For simple level 1 applications only 3 bits of the
color bus are converted into analog RGB signals on
chip.
2.6. Character Generator
Characters are displayed with a 10x10 pixel resolution
in PAL and 10x8 pixel resolution in NTSC mode. Pixel
clock is 10.125 MHz, derived from the main clock of
20.25 MHz. To get 10-bit pixel information two memory
cycles are needed. The character font is part of the
mask-programmable ROM, but supplied with its own
bus structure (see Fig. 4–1). By this means the data
transfer between character ROM and teletext display
controller does not stop the CPU, which is important in
the case of doubled line frequency.
Both bus structures are connected via a memory inter-
face which allows cross-connections using DMA or wait
cycles. As the number of addressable characters is
1024, the maximum character font size is 12800 byte. In
this case part of the character font can be shifted into the
program ROM which causes DMA cycles. Therefore
only less frequently used characters should be placed
into the program ROM. Vice versa seldom used CPU
code can be put into the character ROM.
The WST specification defines a number of 7-bit code
tables, which are filled with 96 characters only. In the G0
code table some characters have several language de-
pendent variations. Additionally characters from the G0
code table can be combined with diacritical marks from
the G2 code table (row 26). Thus it is not possible to sim-
ply transform the code tables into a continuous font
ROM without getting unused ROM space and multiple
defined character fonts.
The character ROM is optimized by reorganizing the
code table structure of the WST specification. The whole
character font is subdivided into blocks of 32 characters
which are mapped to the WST character sets via a mask
programmable mapping ROM (see Fig. 4–5). The char-
acter set selection is done via software.
2.7. OSD Layer
Apart from the WST layer, there is also one additional
OSD layer on chip. The OSD layer accesses the CPU
memory via DMA to read text and character font infor-
mation. The RGB outputs of the OSD layer can have
higher priority than the WST layer outputs. Thus it is pos-
sible to overlay the teletext display with an additional lay-
er for user guidance (see Fig. 2–3).
相關PDF資料 |
PDF描述 |
|---|---|
| TPU3035PO | TELETEXT DECODER, PDIP52 |
| TPU3035PQ | TELETEXT DECODER, PQCC44 |
| TPU3050PK | TELETEXT DECODER, PDIP40 |
| TPU3050PO | TELETEXT DECODER, PDIP52 |
| TPU3050PQ | TELETEXT DECODER, PQCC44 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TPU304 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | JFET | P-CHANNEL | 30MA I(DSS) | TO-226AA |
| TPU3040 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Teletext Processors |
| TPU3040(DIP40) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Teletext Circuit |
| TPU3040(PDIP40) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| TPU3040(PSDIP52) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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