TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
5
Micronas
Table 1–1, continued
TPU
3035
3040
3050
Display
No. of different characters
512
No. of national language
character sets
16
Character matrix size
10x10
No. of display rows
> 26
Pixel graphics
–
16:9 display
(25% shrink)
–
x
1/2 screen display
(50% shrink)
–
x
1/2 screen 16:9 display
(62.5% shrink)
–
x
32 kHz mode
–
x
Non-interlace display
x
50/60 Hz display
x
100/120 Hz display
–
x
Scrolling vertical
x
Scrolling horizontal
–
Double height page display
x
Status row single height
x
Two page display side by
side
–
Stable (line locked) display
with noisy video
x
Display synchronized by
input video
–
75 Ohm output
–
Half contrast RGB out
x
RGB level adjustable
(externally)
–
Level 3
DRCS
–
Level 2
CLUT
D3000
Level 2
double width
x
Level 2
double height
x
Level 2
full screen color
x
TPU
3035
3040
3050
OSD – layer independent
x
Display priority via
software-ID
D3000
RGB input from SCART and
Fast Blank interface
x
Hardware cursor
–
Memory
No. of pages on-chip
–
No. of pages off-chip
112
2032
Minimum DRAM (ext.)
256 Kbit
Maximum DRAM (ext.)
1 Mbit
16 Mbit
DRAM organization
1 bit
DRAM access time
(page mode)
90 ns
Minimum SRAM (ext.)
–
256 Kbit
Maximum SRAM (ext.)
–
1 Mbit
SRAM organization
–
8 bit
SRAM access time
–
100 ns
Automatic memory/config.
check
x
Variable no. of subpages
(internal subpage manage-
ment)
x
Constant page access time
x
Dyn. pg. storage (data com-
pression)
–
General Product Info
Supply voltage [V]
5
Power dissipation [mW]
250
300
Control bus
I2C
IR decoder and control
–
Software macro interface
x
System clock [MHz]
20.25
Package
PDIP40
PLCC44
PDIP40
PSDIP52
Technology
0.8
m
CMOS
0.8
m
CMOS
0.8
m
CMOS