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參數(shù)資料
| 型號： | TPU3035PK |
| 元件分類： | 圖文 |
| 英文描述： | TELETEXT DECODER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 56/72頁 |
| 文件大?。?/td> | 347K |
| 代理商： | TPU3035PK |
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PRELIMINARY DATA SHEET
TPU 3035, TPU 3040, TPU 3050
6
Micronas
2. Functional Description
2.1. Conceptional Overview
The basic idea behind the TPU 3040 concept is the re-
placement of random logic by software. The still existing
hardware supports the on-chip CPU in tasks with high
data rates and ineffective software solutions. Typical
tasks of a teletext decoder are listed below (realization
on TPU 3040 in brackets):
– teletext data acquisition
(hardware)
– teletext data decoding
(software)
– page generation
(software)
– page memory management
(software)
– page display
(hardware)
– user interface
(software)
Fig. 2–1 shows the functional block diagram of the
TPU 3040. The software approach is realized using a
65C02 core with RAM and program ROM on chip. Via
the I/O, the CPU is connected to a DRAM interface. The
DRAM contains an acquisition scratch buffer which is
filled automatically by the teletext slicer circuit. After pro-
cessing this scratch buffer, the CPU stores reorganized
teletext lines into the page memory which takes up the
greatest space in the DRAM capacity. A third part of the
DRAM holds WST level 2 display data, which are read
out by the WST layer. The CPU has to generate the dis-
play data by decoding teletext information from the page
memory.
Apart from the WST layer, there is also one additional
on-chip OSD layer. The OSD layer accesses the on-chip
memory to read text and character font information. The
RGB outputs of the OSD layer can have higher priority
than the WST layer outputs. Thus it is possible to overlay
the teletext display with an additional layer for user guid-
ance.
The CPU memory contains RAM, program ROM and
character ROM. The character ROM holds the font data
and is separated from the program ROM to save CPU
time. The CPU can still access the character ROM via
a DMA interface including wait cycles. The WST layer
and the additional OSD layer can also access the CPU
memory via the same DMA interface.
The CPU is supported by some glue logic such as timer,
watchdog and interrupt controller and communicates
with the outside world via the I2C-Bus.
2.2. Teletext Acquisition
The only task of the slicer circuit is to extract teletext lines
from the incoming composite video signal and to store
them into the acquisition scratch buffer of the external
DRAM. No page selection is done at this hardware level.
Two analog sources can be connected, thus it is pos-
sible to receive text from one channel while watching
another on the screen. After clamping and AGC amplifi-
er the analog video signal is converted into binary data.
Sync separation is done by a sync slicer and a horizontal
PLL, which generate the horizontal and vertical timing.
By these means no external sync signals are needed
and any available signal source can be used for teletext
reception.
The teletext information itself is acquired using adaptive
slicers on bit and byte level with soft error detection to
decrease the bit error rate under bad reception condi-
tions. The slicer can be programmed to different bit rates
for reception of PAL, NTSC or MAC world system tele-
text as well as VPS,WSS, or CAPTION signals.
2.3. Teletext Page Management
As a state-of-the-art teletext decoder the TPU 3040 is
able to store and manage a sufficient number of teletext
pages to absorb the annoying transmission cycle times.
The number of available pages is only limited by the
memory size. With an intelligent software and a 16 Mbit
DRAM it is possible to store and to control more than
2000 teletext pages.
The management of such a data base is a typical soft-
ware task and is therefore performed by the 65C02. Us-
ing a fixed length page table with one entry for every pos-
sible page, the software distributes the content of the
acquisition scratch buffer among the page memory. The
page size is fixed to 1 KByte, only ghost rows are
chained in 128-byte segments to avoid unused memory
space.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TPU3035PO | TELETEXT DECODER, PDIP52 |
| TPU3035PQ | TELETEXT DECODER, PQCC44 |
| TPU3050PK | TELETEXT DECODER, PDIP40 |
| TPU3050PO | TELETEXT DECODER, PDIP52 |
| TPU3050PQ | TELETEXT DECODER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TPU304 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | JFET | P-CHANNEL | 30MA I(DSS) | TO-226AA |
| TPU3040 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Teletext Processors |
| TPU3040(DIP40) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Teletext Circuit |
| TPU3040(PDIP40) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| TPU3040(PSDIP52) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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