參數(shù)資料
型號(hào)： TP3076J
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 編解碼器
英文描述： COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications
中文描述： A/MU-LAW, PROGRAMMABLE CODEC, CDIP20
封裝： CERAMIC, DIP-20
文件頁(yè)數(shù)： 9/18頁(yè)
文件大?。?/td> 222K
代理商： TP3076J
Absolute Maximum Ratings
(Note 12)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC
to GND
Voltage at VF
X
I
Voltage at Any Digital Input
7V
V
CC
+0.5V to V
BB
0.5V
V
CC
+0.5V to GND 0.5V
Storage Temperature Range
V
BB
to GND
Current at VF
R
0
Current at Any Digital Output
Lead Temperature
(Soldering, 10 sec.)
65C to +150C
7V
±
100 mA
±
50 mA
300C
Electrical Characteristics
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5V
±
5%, V
= 5V
±
5%; T
= 0C to
+70C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other production
tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V
CC
= +5V, V
BB
= 5V,
T
A
= 25C.
Symbol
Parameter
Conditions
DIGITAL INTERFACES
V
IL
Input Low Voltage
All Digital Inputs (DC Meas.)
V
IH
Input High Voltage
All Digital Inputs (DC Meas.) (Note 13)
V
OL
Output Low Voltage
D
X
1, TS
X
1, and CO, I
L
= 3.2 mA,
All Other Digital Outputs, I
L
= 1 mA
V
OH
Output High Voltage
D
X
1 and CO, I
L
= 3.2 mA,
All Other Digital Outputs (except TS
X
), I
L
= 1 mA
All Digital Outputs, I
L
= 100 μA
I
IL
Input Low Current
I
IH
Input High Current
MR Only
I
OZ
Output Current in
D
X
1, TS
X1
and CO
High Impedance
IL3–IL0 when Selected as Inputs
State (TRI-STATE )
GND
<
V
OUT
<
V
CC
ANALOG INTERFACES
I
VFXI
Input Current, VF
X
I
R
VFXI
Input Resistance
VOS
X
Input Offset Voltage
Transmit Gain = 0 dB
Applied at VF
X
I
Transmit Gain = 25.40 dB
RL
VFRO
Load Resistance
Receive Gain = 0 dB
Receive Gain = 0.5 dB
Receive Gain = 1.2 dB
CL
VFRO
Load Capacitance
RL
VFRO
≥
300
CL
VFRO
from VF
R
O to GND
RO
VFRO
Output Resistance
Steady Zero PCM Code Applied to D
R
1
VOS
R
Output Offset Voltage
Alternating
±
Zero PCM Code Applied
at V
FRO
D
R
1, Maximum Receive Gain
POWER DISSIPATION
I
CC
0
Power Down Current
CCLK, CI, CO = 0.4V, CS = 2.4V
Interface Latches Set as Outputs with No Load,
All Other Inputs Active, Power Amp Disabled
I
BB
0
Power Down Current
As Above
I
CC
1
Power Up Current
CCLK, CI, CO = 0.4V, CS = 2.4V
No Load on Power Amp
Interface Latches Set as Outputs with No Load
I
BB
1
Power Up Current
As Above
I
CC
2
Power Down Current
As Above, Power Amp Enabled
I
BB
2
Power Down Current
As Above, Power Amp Enabled
Min
Typ
Max
Units
0.7
V
V
V
2.0
0.4
2.4
V
V
CC
0.5
10
10
10
V
μA
μA
Any Digital Input, GND
<
V
IN
<
V
IL
Any Digital Input, except MR, V
IH
<
V
IN
<
V
CC
10
10
100
10
10
μA
3.3V
<
VF
X
I
<
3.3V
3.3V
<
VF
X
I
<
3.3V
1.0
1.0
1.0
μA
M
mV
mV
200
10
15k
600
300
200
pF
1.0
3.0
200
mV
200
0.1
0.6
mA
0.1
0.3
mA
8.0
11.0
mA
8.0
2.0
2.0
11.0
3.0
3.0
mA
mA
mA
Note 12:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
www.national.com
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