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參數(shù)資料
| 型號： | TP3076J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications |
| 中文描述： | A/MU-LAW, PROGRAMMABLE CODEC, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 222K |
| 代理商： | TP3076J |
Functional Description
(Continued)
The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.
POWER-DOWN STATE
Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the “P” bit
set to “1” as indicated in Table 1 It is recommended that the
chip be powered down before writing any additional instruc-
tions. In the power-down state, all non-essential circuitry is
de-activated and the D
X
1 output is in the high impedance
TRI-STATE condition.
The data stored in the Gain Control registers, the LDR and
ILR,
and
all
control
bits
power-down state unless changed by writing new data via
the serial control port, which remains active. The outputs of
the Interface Latches also remain active, maintaining the
ability to monitor and control the SLIC.
remain
unchanged
in
the
TRANSMIT FILTER AND ENCODER
The Transmit section input, VF
I, is a high impedance input.
No external components are necessary to set the gain. Fol-
lowing this is a programmable gain/attenuation amplifier
which is controlled by the contents of the Transmit Gain Reg-
ister (see Programmable Functions section). An active
pre-filter then precedes the 3rd order high-pass and 5th or-
der low-pass switched capacitor filters. The A/D converter
has a compressing characteristic according to the standard
CCITT A or μ255 coding laws, which must be selected by a
control instruction during initialization (see Table 1and Table
2). A precision on-chip voltage reference ensures accurate
and highly stable transmission levels.Any offset voltage aris-
ing in the gain-set amplifier, the filters or the comparator is
canceled by an internal auto-zero circuit.
Each encode cycle begins immediately following the as-
signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 μs (due to
the Transmit Filter) plus 125 μs (due to encoding delay),
which totals 290 μs. Data is shifted out on D
1 during the se-
lected time slot on eight rising edges of BCLK.
DECODER AND RECEIVER FILTER
PCM data is shifted into the Decoder’s Receive PCM Regis-
ter via the D
1 pin during the selected time-slot on the 8 fall-
ing edges of BCLK. The Decoder consists of an expanding
DAC with eitherAor μ255 law decoding characteristic, which
is selected by the same control instruction used to select the
Encode law during initialization. Following the Decoder is a
5th order low-pass switched capacitor filter with integral Sin
x/x correction for the 8 kHz sample and hold. A program-
mable gain amplifier, which must be set by writing to the Re-
ceive Gain Register, is included, and finally a Power Ampli-
fier capable of driving a 300
load to
±
3.5V, a 600
load to
±
3.8V or a 15 k
load to
±
4.0V at peak overload.
TABLE 1. Programmable Register Instructions
Function
Byte 1
(Notes 1, 2, 3)
5
4
X
X
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
1
Byte 2
(Note 1)
4
None
See Table 2
See Table 2
See Table 4
See Table 4
See Table 3
See Table 3
See Table 8
See Table 8
See Table 7
See Table 7
See Table 6
See Table 6
See Table 6
See Table 6
7
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
6
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
3
X
0
0
1
1
0
0
0
0
1
1
1
1
0
0
2
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
5
3
2
1
0
Single Byte Power-Up/Down
Write Control Register
Read-Back Control Register
Write to Interface Latch Register
Read Interface Latch Register
Write Latch Direction Register
Read Latch Direction Register
Write Receive Gain Register
Read Receive Gain Register
Write Transmit Gain Register
Read Transmit Gain Register
Write Receive Time-Slot/Port
Read-Back Receive Time-Slot/Port
Write Transmit Time-Slot/Port
Read-Back Transmit Time-Slot/Port
Note 1:
Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X = don’t care.
Note 2:
“P” is the power-up/down control bit, see Power-up/Down Control section. (“0” = Power Up, “1” = Power Down)
Note 3:
Other register address codes are invalid and should not be used.
A decode cycle begins immediately after the assigned re-
ceive timeslot, and 10 μs later the Decoder DAC output is
updated. The total signal delay is 10 μs plus 120 μs (filter de-
lay) plus 62.5 μs (
1
2
frame) which gives approximately 190
μs.
PCM INTERFACE
The FS
and FS
frame sync inputs determine the begin-
ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see Table 2). Non-delayed data mode is
similar to long-frame timing on the TP3050/60 series of de-
www.national.com
3
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相關代理商/技術參數(shù) |
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| TP3076N-G/NOPB | 功能描述:IC INTERFACE PCM COMBO II 20-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:COMBO®II 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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| TP309 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| TP3094 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Quad PCM Codec/Filter |
| TP3094V | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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