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參數(shù)資料
| 型號： | TP3076J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications |
| 中文描述： | A/MU-LAW, PROGRAMMABLE CODEC, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 222K |
| 代理商： | TP3076J |
Timing Specifications
(Continued)
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5V
±
5%; V
= 5V
±
5%; T
= 0C to
+70C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other production
tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V
CC
= +5V, V
BB
= 5V,
T
= 25C.
All timing parameters are measured at V
= 2.0V and V
= 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
PCM INTERFACE TIMING
High to Data Valid
Applies if FS
X/R
Rises Later Than
BCLK Rising Edge in Non-Delayed Data
Mode Only
t
SDB
Setup Time, D
R
1
Valid to BCLK Low
t
HBD
Hold Time, BCLK
Low to D
R
1 Invalid
SERIAL CONTROL PORT TIMING
f
CCLK
Frequency of CCLK
t
WCH
Period of CCLK High
Measured from V
IH
to V
IH
t
WCL
Period of CCLK Low
Measured from V
IL
to V
IH
t
RC
Rise Time of CCLK
Measured from V
IL
to V
IH
t
FC
Fall Time of CCLK
Measured of V
IH
to V
IL
t
HCS
Hold Time, CCLK Low
CCLK1
to CS Low
t
HSC
Hold Time, CCLK
CCLK8
Low to CS High
t
SSC
Setup Time, CS
Transition to CCLK Low
t
SSC0
Setup Time, CS
To Insure CO is Not Enabled
Transition to CCLK High
for Single Byte
t
SDC
Setup Time, CI
Data In to CCLK Low
t
HCD
Hold Time, CCLK
Low to CO Invalid
t
DCD
Delay Time, CCLK High
Load = 100 pF Plus 2 LSTTL Loads
to CO Data Out Valid
t
DSD
Delay Time, CS Low
Applies Only if Separate
to CO Valid
CS Used for Byte 2
t
DDZ
Delay Time, CS or 9th CCLK
Applies to Earlier of CS
High to CO High Impedance
High or 9th CCLK High
INTERFACE LATCH TIMING
t
SLC
Setup Time, IL to
Interface Latch Inputs Only
CCLK 8 of Byte 1
t
HCL
Hold Tme, IL Valid from
8th CCLK Low (Byte 1)
t
DCL
Delay Time CCLK8 of
Interface Latch Outputs Only
Byte 2 to IL
C
L
= 50 pF
Conditions
Min
Typ
Max
Units
80
ns
30
ns
15
ns
2048
kHz
ns
ns
ns
ns
ns
160
160
50
50
10
100
ns
60
ns
60
ns
50
ns
50
ns
80
ns
80
ns
15
80
ns
100
ns
50
ns
200
ns
Note 14:
Applies only to MCLK Frequencies
≥
1.536 MHz. At 512 kHz a 50:50
±
2% Duty Cycle must be used.
www.national.com
11
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