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參數(shù)資料
| 型號： | TP3076J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications |
| 中文描述： | A/MU-LAW, PROGRAMMABLE CODEC, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 222K |
| 代理商： | TP3076J |
Electrical Characteristics
(Continued)
Note 13:
See definitions and timing conventions section.
Timing Specifications
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5V
±
5%; V
= 5V
±
5%; T
= 0C to
+70C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other production
tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V
CC
= +5V, V
BB
= 5V,
T
= 25C.
All timing parameters are measured at V
= 2.0V and V
= 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
MASTER CLOCK TIMING
f
MCLK
Frequency of MCLK
Selection of Frequency is Programmable
(See Table 5)
Conditions
Min
Typ
Max
Units
512
1536
1544
2048
4096
kHz
kHz
kHz
kHz
kHz
ns
ns
ns
ns
ns
t
WMH
t
WML
t
RM
t
FM
t
HBM
Period of MCLK High
Period of MCLK Low
Rise Time of MCLK
Fall Time of MCLK
HOLD Time, BCLK LOW
to MCLK HIGH
Period of FS
X
or FS
R
Low
PCM INTERFACE TIMING
f
BCLK
Frequency of BCLK
Measured from V
IH
to V
IH
(Note 14)
Measured from V
IL
to V
IL
(Note 14)
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
80
80
30
30
50
t
WFL
Measured from V
IL
to V
IL
1
MCLK
Period
May Vary from 64 kHz to 4096 kHz
in 8 kHz Increments
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
64
4096
kHz
t
WBH
t
WBL
t
RB
t
FB
t
HBF
Period of BCLK High
Period of BCLK Low
Rise Time of BCLK
Fall Time of BCLK
Hold Time, BCLK Low
to FS
X/R
High or Low
Setup Time, FS
X/R
High to BCLK Low
Delay Time, BCLK High
to Data Valid
Delay Time, BCLK Low to D
X
1
Disabled if FS
X
Low, FS
X
Low to
D
X
1 disabled if 8th BCLK
Low, or BCLK High to D
X
1
Disabled if FS
X
High
Delay Time, BCLK High to
TS
X
Low if FS
X
High, or
FS
X
High to TS
X
Low if
BCLK High (Nondelayed mode); BCLK
High to TS
X
Low (delayed data mode)
TRI-STATE Time, BCLK Low to
TS
X
High if FS
X
Low, FS
X
Low
to TS
X
High if 8th BCLK Low, or
BCLK High to TS
X
High if FS
X
High
Delay Time, FS
X/R
80
80
ns
ns
ns
ns
ns
30
30
30
t
SFB
30
ns
t
DBD
Load = 100 pF Plus 2 LSTTL Loads
80
ns
t
DBZ
D
X
1 disabled is measured
at V
OL
or V
OH
according
to Figure 5
15
80
ns
t
DBT
Load = 100 pF Plus 2 LSTTL Loads
60
ns
t
ZBT
15
60
ns
t
DFD
Load = 100 pF Plus 2 LSTTL Loads,
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