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參數(shù)資料
| 型號(hào)： | TP3076J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications |
| 中文描述： | A/MU-LAW, PROGRAMMABLE CODEC, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 6/18頁(yè) |
| 文件大小： | 222K |
| 代理商： | TP3076J |
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Programmable Functions
(Continued)
TABLE 6. Time-Slot and Port Assignment Instruction
Bit Number and Name
5
T
5
(Note 7)
X
Function
7
6
4
T
4
3
T
3
2
T
2
1
T
1
0
T
0
EN
PS
(Note 6)
1
0
X
X
X
X
X
Disable D
X
1 Output (Transmit Instruction)
Disable D
R
1 Input (Receive Instruction)
Enable D
X
1 Output (Transmit Instruction)
Enable D
R
1 Input (Transmit Instruction)
1
1
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Note 6:
The “PS” bit MUST be set to “1” for both transmit and receive for the TP3076.
Note 7:
T5 is the MSB of the time-slot assignment bit field. Time-slot bits should be set to “000000” for both transmit and receive when operating in non-delayed data
timing mode.
TIME-SLOT ASSIGNMENT
COMBO II can operate in either fixed time-slot or time-slot
assignment mode for selecting the Transmit and Receive
PCM time-slots. Following power-on, the device is automati-
cally in Non-Delayed Timing mode, in which the time-slot al-
ways begins with the leading (rising) edge of frame sync in-
puts FS
and FS
. Time-Slot Assignment may only be used
with Delay Data timing; see Figure 4 FS
and FS
may
have any phase relationship with each other in BCLK period
increments.
Alternatively, the internal time-slot assignment counters and
comparators can be used to access any time-slot in a frame,
using the frame sync inputs as marker pulses for the begin-
ning of transmit and receive time-slot 0. In this mode, a
frame may consist of up to 64 time-slots of 8 bits each. A
time-slot is assigned by a 2-byte instruction as shown in
Table 1 and Table 6 The last 6 bits of the second byte indi-
cate the selected time-slot from 0–63 using straight binary
notation. When writing a time-slot and port assignment reg-
ister, if the PCM interface is currently active, it is immediately
deactivated to prevent possible bus clashes. A new assign-
ment becomes active on the second frame following the end
of the Chip-Select for the second control byte. Rewriting of
the register contents should not be performed during the
talking period of a connection to prevent waveform distortion
caused by loss of a sample which will occur with each regis-
ter write. The “EN” bit allows the PCM input, D
R
1, or output,
D
X
1, as appropriate, to be enabled or disabled.
Time-Slot Assignment mode requires that the FS
and FS
R
pulses conform to the delayed data timing format shown in
Figure 4
PORT SELECTION
On the TP3076, the “PS” bit MUST always be set to 1.
Table 6 shows the format for the second byte of both trans-
mit and receive time-slot and port assignment instructions.
TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in Table 1
and Table 7 This corresponds to a range of 0 dBm0 levels at
VF
I between 1.375 Vrms and 0.074 Vrms (equivalent to
+5.0 dBm to 20.4 dBm in 600
).
To calculate the binary code for byte 2 of this instruction for
any desired input 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
200 x log
10
(V/0.07299)
and convert to the binary equivalent. Some examples are
given in Table 7 A complete tabulation is given in Appendix
I of AN-614.
It should be noted that the Transmit (idle channel) Noise and
Transmit Signal to Total Distortion are both specified with
transmit gain set to 0 dB (gain register set to all ones). At
high transmit gains there will be some degradation in noise
performance for these parameters. See Application Note
AN-614 for more information on this subject.
TABLE 7. Byte 2 of Transmit Gain Instruction
Bit Number
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
—
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
0 dBm0 Test Level (Vrms)
at VF
X
I
No Output (Note 8)
0.074
0.075
—
1.359
1.375
Note 8:
Analog signal path is cut off, but D
X
remains active and will output
codes representing idle noise.
RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB steps by writ-
ing to the Receive Gain Register as defined in Table 1 and
Table 8 Note the following restrictions on output drive capa-
bility:
1.
0 dBm0 levels
≤
1.96 Vrms at VF
O may be driven into
a load of
≥
15 k
to GND; Receive Gain set to 0 dB (gain
register set to all ones).
2.
0 dBm0 levels
≤
1.85 Vrms at VF
O may be driven into
a load of
≥
600
to GND; Receive Gain set to 0.5 dB.
3.
0 dBm0 levels
≤
1.71 Vrms at VF
O may be driven into
a load of
≥
300
to GND. Receive Gain set to 1.2 dB.
To calculate the binary code for byte 2 of this instruction for
any desired output 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
200 x log
10
(V/0.1043)
and convert to the binary equivalent. Some examples are
given in Table 8 A complete tabulation is given in Appendix I
or AN-614.
www.national.com
6
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| TP3076 | COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications |
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| TP3094V | Quad PCM Codec/Filter |
| TP3155V | TP3155 Time Slot Assignment Circuit |
| TP3155N | TP3155 Time Slot Assignment Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3076N-G/NOPB | 功能描述:IC INTERFACE PCM COMBO II 20-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:COMBO®II 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| TP308 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| TP309 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| TP3094 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Quad PCM Codec/Filter |
| TP3094V | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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