參數(shù)資料
型號： TMX320F2812ZHHS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 93/147頁
文件大小： 2021K
代理商： TMX320F2812ZHHS
Electrical Specifications
93
June 2004
SPRS257
t
w(RSL1)
t
h(XPLLDIS)
t
h(XMP/MC)
t
h(boot-mode)
(
see Note C)
V
DDIO
, V
DDAn
,
V
DDAIO
(3.3 V)
(See Note A)
XCLKIN
2.5 V
0.3 V
X1
XRS
XF/XPLLDIS
XMP/MC
Boot-Mode Pins
V
DD
, V
DD1
(1.8 V (or 1.9 V))
XCLKOUT
I/O Pins
User-Code Dependent
User-Code Dependent
User-Code Dependent
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
GPIO Pins as Input
XPLLDIS Sampling
GPIOF14
XCLKIN/8 (See Note B)
GPIO Pins as Input (State Depends on Internal PU/PD)
t
OSCST
(Don’t Care)
(Don’t Care)
User-Code Dependent
Address/Data/
Control
Address/Data Valid. Internal Boot-ROM Code Execution Phase
User-Code Execution Phase
NOTES: A. V
DDAn
V
DDA1
/V
DDA2
and AV
DDREFBG
B. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This
explains why XCLKOUT = XCLKIN/8 during this phase.
C. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then
samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot
code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM
execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on
the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL
enabled.
D. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least
1 V and 3.3-V supply reaches 2.5 V.
t
d(EX)
See Note D
t
su(XPLLDIS)
Figure 6
6. Power-on Reset in Microcomputer Mode (XMP/MC = 0)
A
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