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參數(shù)資料
| 型號： | TMX320F2812ZHHS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | TMS320R2811, TMS320R2812 Digital Signal Processors |
| 中文描述： | TMS320R2811，TMS320R2812數(shù)字信號處理器 |
| 文件頁數(shù)： | 118/147頁 |
| 文件大小： | 2021K |
| 代理商： | TMX320F2812ZHHS |
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Electrical Specifications
118
June 2004
SPRS257
6.25
External Interface Ready-on-Read Timing With One External Wait State
Table 6
29. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
d(XCOHL-XRDH
t
h(XA)XZCSH
t
h(XA)XRD
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
1
3
2
1
1
ns
ns
ns
ns
ns
ns
2
2
Hold time, address valid after XRD inactive high
ns
Table 6
30. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
t
a(A)
t
a(XRD)
t
su(XD)XRD
t
h(XD)XRD
LR = Lead period, read access. AR = Active period, read access. See Table 6
24.
Access time, read data from address valid
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
(LR + AR)
14
AR
12
ns
ns
ns
ns
12
0
Table 6
31. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
§
MIN
MAX
UNIT
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
e(XRDYsynchH)
t
su(XRDYsynchH)XCOHL
t
h(XRDYsynchH)XZCSH
§
The first XREADY (Synch) sample occurs with respect to E in Figure 6
28:
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each t
c(XTIM)
until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE +n
1) t
c(XTIM)
t
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
15
12
ns
ns
ns
ns
ns
3
15
0
Table 6
32. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
t
su(XRDYAsynchL)XCOHL
t
h(XRDYAsynchL)
t
e(XRDYAsynchH)
t
su(XRDYAsynchH)XCOHL
t
h(XRDYasynchH)XZCSH
The first XREADY (Asynch) sample occurs with respect to E in Figure 6
29:
E = (XRDLEAD + XRDACTIVE
2) t
c(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE
3 +n) t
c(XTIM)
t
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
11
8
ns
ns
ns
ns
ns
3
11
0
A
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