參數資料
型號: TMX320F2812ZHHS
廠商: Texas Instruments, Inc.
元件分類: 數字信號處理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812數字信號處理器
文件頁數: 48/147頁
文件大?。?/td> 2021K
代理商: TMX320F2812ZHHS
Functional Overview
48
June 2004
SPRS257
3.7.5
Watchdog Block
The watchdog block on R281x is identical to the one used on the 240x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter
has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog
counter. Figure 3
10 shows the various functional blocks within the watchdog module.
/512
OSCCLK
WDCR (WDPS(2:0))
WDCLK
WDCNTR(7:0)
WDKEY(7:0)
Bad Key
Good Key
1
0
1
WDCR (WDCHK(2:0))
Bad
WDCHK
Key
WDCR (WDDIS)
Clear Counter
SCSR (WDENINT)
Watchdog
Prescaler
Generate
Output Pulse
(512 OSCCLKs)
8-Bit
Watchdog
Counter
CLR
WDRST
WDINT
Watchdog
55 + AA
Key Detector
XRS
Core-reset
NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles.
WDRST
(See Note A)
Internal
Pullup
Figure 3
10. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional
is the watchdog. The Watchdog module will run off the PLL clock or the oscillator clock. The WDINT signal
is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7.6,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is
the WATCHDOG.
3.7.6
Low-Power Modes Block
The low-power modes on R281x are similar to the 240x devices. Table 3
14 summarizes the various modes.
A
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