參數資料
型號: TMX320F2812ZHHS
廠商: Texas Instruments, Inc.
元件分類: 數字信號處理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812數字信號處理器
文件頁數: 29/147頁
文件大?。?/td> 2021K
代理商: TMX320F2812ZHHS
Functional Overview
29
June 2004
SPRS257
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(Enabled if MP/MC = 0)
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(4K
×
16, Protected)
Block
Start Address
L
(
0x00 0000
M0 Vector
RAM (32
×
32)
(Enabled if VMAP = 0)
Data Space
Prog Space
M0 SARAM (1K
×
16)
M1 SARAM (1K
×
16)
ííííííí
ííííííí
ííííííí
Reserved
Peripheral Frame 0
(2K
×
16)
PIE Vector - RAM
(256
×
16)
(Enabled if VMAP
0x00 0040
0x00 0400
0x00 0800
íííííííííííí
Reserved
L0 SARAM (4K
×
16,)
Peripheral Frame 1
ííííííí
ííííííí
L1 SARAM (4K
×
16)
Reserved
Peripheral Frame 2
(4K
×
16, Protected)
Reserved
×
Reserved
BROM Vector - ROM (32
×
32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
0x00 0D00
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
H
(
P
On-Chip Memory
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. The passwords are set to all ones.
LEGEND:
L2 SARAM (1K
×
16)
L3 SARAM (1K
×
16)
0x00 A400
0x00 A800
Figure 3
3. R2811 Memory Map (See Notes A through F)
A
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