參數(shù)資料
型號： TMX320DM648ZUT900
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 70/166頁
文件大?。?/td> 1341K
代理商： TMX320DM648ZUT900
www.ti.com
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6.6 Enhanced Direct Memory Access (EDMA3) Controller
6.6.1
EDMA3 Channel Synchronization Events
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the DM648 device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses. These are summarized as follows:
Transfer to/from on-chip memories
–
DSP L1D memory
–
DSP L2 memory
Transfer to/from external storage
–
DDR2 SDRAM
–
Synchronous/Asynchronous EMIF (EMIFA)
Transfer to/from peripherals/hosts
–
VLYNQ
–
HPI
–
McASP
–
UART
–
Video Port 0/1/2/3/4
–
Timer 0/1/2/3
–
SPI
–
I2C
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 6-13
lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. For the DM648 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the
EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers
(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,
captured, processed, linked, chained, and cleared, etc., see the
TMS320DM647/DM648 DSP Enhanced
DMA (EDMA) Controller User's Guide
(literature number
SPRUEL2
).
Table 6-13. EDMA Channel Synchronization Events
TPCC
CHANN
EL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DEFAULT
EVENT#
BINARY
DEFAULT EVENT
TPCC
CHANNEL
DEFAULT
EVENT #
BINARY
DEFAULT EVENT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
HPI/PCI : DSPINT
TIMER0 : TINT0L
TIMER0 : TINT0H
TIMER2 : TINT2L
TIMER2 : TINT2H
TIMER3 : TINT3L
TIMER3 : TINT3H
IMCOP: IMXINT
IMCOP: VLCDINT
IMCOP: DSQINT
McASP: AXEVTE
McASP: AXEVTO
McASP: AXEVT
McASP: AREVTE
McASP: AREVTO
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110
010 0111
010 1000
010 1001
010 1010
010 1011
010 1100
010 1101
010 1110
VP2EVTYA
VP2EVTUA
VP2EVTVA
VP2EVTYB
VP2EVTUB
VP2EVTVB
VP3EVTYA
VP3EVTUA
VP3EVTVA
VP3EVTYB
VP3EVTUB
VP3EVTVB
ICREVT
ICXEVT
SPI: SPIXEVT
Peripheral Information and Electrical Specifications
70
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