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6.23 IEEE 1149.1 JTAG
6.23.1 JTAG Peripheral Register Description(s) – JTAG ID Register
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The JTAG
(2)
interface is used for BSDL testing and emulation of the DM647/DM648 devices.
TRST needs to be released only when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and
must
be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
For maximum reliability, DM647/DM648 devices include an internal pulldown (IPD) on the TRST pin to
make certain that TRST will always be asserted upon power up and the device's internal emulation logic
will always be properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
(2)
Table 6-84. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
0x0204 9018
JTAGID
JTAG Identification Register
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
DM647/DM648 devices, the JTAG ID register resides at address location 0x0204 9018. The register hex
value for DM647/DM648 is: 0x0B77 A02F . For the actual register bit names and their associated bit field
descriptions, see
Figure 6-47
and
Table 6-85
.
31-28
27-12
11-1
0
VARIANT (4-Bit)
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-0000
R-1011 0111 0111 1010
R-0000 0010 111
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-47. JTAGID Register (0x0204 9018) Description
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