參數(shù)資料
型號: TMX320DM648ZUT900
廠商: Texas Instruments, Inc.
英文描述: Digital Media Processor
中文描述: 數(shù)字媒體處理器
文件頁數(shù): 110/166頁
文件大?。?/td> 1341K
代理商: TMX320DM648ZUT900
www.ti.com
P
VPxCLKINx
VPxCLKOUTx
[VCLK2P = 0]
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
VPxCTLx,V
PxD[19:0]
(Outputs)
VPxCTLx
(Input)
5
7
1
3
2
6
8
9
13
10
14
11
12
15
16
4
4
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-40. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx
(1)(2)
(see
Figure 6-24
)
-720
-900
NO.
PARAMETER
UNIT
MIN
MAX
V + 0.7
VH + 0.7
VL + 0.7
1
2
3
4
5
6
7
8
9
t
c(VKO)
t
w(VKOH)
t
w(VKOL)
t
t(VKO)
t
d(VKIH-VKOH)
t
d(VKIL-VKOL)
t
d(VKIH-VKOL)
t
d(VKIL-VKOH)
t
d(VKIH-VPOUTV)
t
d(VKIH-VPOUTIV)
t
d(VKOH-VPOUTV)
t
d(VKOH-VPOUTIV)
Cycle time, VPxCLKOUTx
Pulse duration, VPxCLKOUTx high
Pulse duration, VPxCLKOUTx low
Transition time, VPxCLKOUTx
Delay time, VPxCLKINx high to VPxCLKOUTx high
(3)
Delay time, VPxCLKINx low to VPxCLKOUTx low
(3)
Delay time, VPxCLKINx high to VPxCLKOUTx low
Delay time, VPxCLKINx low to VPxCLKOUTx high
Delay time, VPxCLKINx high to VPxOUT valid
(4)
Delay time, VPxCLKINx high to VPxOUT invalid
(4)
Delay time, VPxCLKOUTx high to VPxOUT valid
(1)(4)
Delay time, VPxCLKOUTx high to VPxOUT invalid
(1)(4)
V – 0.7
VH – 0.7
VL – 0.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.8
5.7
5.7
5.7
5.7
1.1
1.1
1.1
1.1
9
10
11
12
1.7
4.3
–0.2
Figure 6-24. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx
(1)
(2)
(3)
(4)
V = the video input clock (VPxCLKINx) period in ns.
VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
Assuming non-inverted VPxCLKOUTx signal.
VPxOUT consists of VPxCTLx and VPxD[19:0]
110
Peripheral Information and Electrical Specifications
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