參數(shù)資料
型號(hào)： TMX320DM648ZUT900
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 57/166頁
文件大小： 1341K
代理商： TMX320DM648ZUT900
www.ti.com
P
6.1.3
Timing Parameters and Board Routing Analysis
1
2
3
4
5
6
7
8
10
11
AECLKOUT
(Output from DSP)
AECLKOUT
(Input to External Device)
Control Signals
(A)
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals
(B)
(Output from External Device)
Data Signals
(B)
(Input to DSP)
9
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The timing parameter values specified in this data sheet do
not
include delays by board routings. As a
good board design practice, such delays must
always
be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the
Using IBIS Models for Timing
Analysis Application Report
(literature number
SPRA839
). If needed, external logic hardware such as
buffers may be used to compensate for any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external
device and from the external device to the DSP. This round-trip delay tends to negatively impact the input
setup time margin, but also tends to improve the input hold time margins (see
Table 6-1
and
Figure 6-4
).
Figure 6-4
represents a general transfer between the DSP and an external device. The figure also
represents board route delays and how they are perceived by the DSP and the external device.
Table 6-1. Board-Level Timing Example
(see
Figure 6-4
)
NO.
1
2
3
4
5
6
7
8
9
10
11
DESCRIPTION
Clock route delay
Minimum DSP hold time
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
A.
B.
Control signals include data for writes.
Data signals are generated during Reads from an external device.
Figure 6-4. Board-Level Input/Output Timings
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Peripheral Information and Electrical Specifications
57
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參數(shù)描述
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TMX320DM8148CCYE2 制造商:Texas Instruments 功能描述:
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